Ignition delay studies on hydrocarbon fuel with and without additives

Single pulse shock tube facility has been developed in the High Temperature Chemical Kinetics Lab, Aerospace Engineering Department, to carry out ignition delay studies and spectroscopic investigations of hydrocarbon fuels. Our main emphasis is on measuring ignition delay through pressure rise and by monitoring CH emission for various jet fuels and finding suitable additives for reducing the delay. Initially the shock tube was tested and calibrated by measuring the ignition delay of C2H6-O2 mixture. The results are in good agreement with earlier published works. Ignition times of exo-tetrahdyrodicyclopentadiene (C10H16), which is a leading candidate fuel for scramjet propulsion has been studied in the reflected shock region in the temperature range 1250 - 1750 K with and without adding Triethylamine (TEA). Addition of TEA results in substantial reduction of ignition delay of C10H16.

Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding

Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper we introduce a new energy-efficient fault-tolerant CMP architecture known as Redundant Execution using Critical Value Forwarding (RECVF). RECVF is based on two observations: (i) forwarding critical instruction results from the leading to the trailing core enables the latter to execute faster, and (ii) this speedup can be exploited to reduce energy consumption by operating the trailing core at a lower voltage-frequency level. Our evaluation shows that RECVF consumes 37% less energy than conventional dual modular redundant (DMR) execution of a program. It consumes only 1.26 times the energy of a non-fault-tolerant baseline and has a performance overhead of just 1.2%.

The effect of malathion, an organophosphate, on the plasma FSH, 17 beta-estradiol and progesterone concentrations and acetylcholinesterase activity and conception in dairy cattle

The effect of malathion on jugular plasma concentrations of follicle-stimulating hormone (FSH), estradiol (E2), progesterone (P4) and acetylcholinesterase (AchE) on conception in dairy cattle during a cloprostenol (prostaglandin F2-alpha analogue, PG)-induced estrus was studied. Malathion (1 mg/kg, intraruminally) given at the onset of estrus (48 h after PG) did not alter the plasma FSH or E2 concentrations but significantly (P < 0.05) inhibited plasma P4 concentration. The mean P4 concentration in the malathion-treated group on days 8 and 12 were 0.8 +/- 0.4 and 1.0 +/- 0.5 ng/ml, as compared to 2.6 +/- 0.0 and 2.4 +/- 0.3 ng/ml in the control group. There was a nonsignificant (P > 0.05) inhibition of plasma AchE activity in malathion-treated cattle. Conception was 16.6% in malathion-treated cows and 50% in controls. Inhibition of progesterone secretion and poor conception occurred after the single intraruminal dose of malathion at the onset of estrus.

Realizing a flexible constraint length Viterbi decoder for software radio on a de Bruijn interconnection network

Building flexible constraint length Viterbi decoders requires us to be able to realize de Bruijn networks of various sizes on the physically provided interconnection network. This paper considers the case when the physical network is itself a de Bruijn network and presents a scalable technique for realizing any n-node de Bruijn network on an N-node de Bruijn network, where n < N. The technique ensures that the length of the longest path realized on the network is minimized and that each physical connection is utilized to send only one data item, both of which are desirable in order to reduce the hardware complexity of the network and to obtain the best possible performance.

Fault-Tolerant Average Execution Time Optimization for General Purpose Multi-Processor System-on Chips

Fault-tolerance is due to the semiconductor technology development important, not only for safety-critical systems but also for general-purpose (non-safety critical) systems. However, instead of guaranteeing that deadlines always are met, it is for general-purpose systems important to minimize the average execution time (AET) while ensuring fault-tolerance. For a given job and a soft (transient) error probability, we define mathematical formulas for AET that includes bus communication overhead for both voting (active replication) and rollback-recovery with checkpointing (RRC). And, for a given multi-processor system-on-chip (MPSoC), we define integer linear programming (ILP) models that minimize AET including bus communication overhead when: (1) selecting the number of checkpoints when using RRC, (2) finding the number of processors and job-to-processor assignment when using voting, and (3) defining fault-tolerance scheme (voting or RRC) per job and defining its usage for each job. Experiments demonstrate significant savings in AET.

Power Efficient Redundant Execution for Chip Multiprocessor

This paper describes the design of a power efficient microarchitecture for transient fault detection in chip multiprocessors (CMPs) We introduce a new per-core dynamic voltage and frequency scaling (DVFS) algorithm for our architecture that significantly reduces power dissipation for redundant execution with a minimal performance overhead. Using cycle accurate simulation combined with a simple first order power model, we estimate that our architecture reduces dynamic power dissipation in the redundant core by an mean value of 79% and a maximum of 85% with an associated mean performance overhead of only 1:2%

Streaming FFT on REDEFINE-v2: An Application-Architecture Design Space Exploration

In this paper we explore an implementation of a high-throughput, streaming application on REDEFINE-v2, which is an enhancement of REDEFINE. REDEFINE is a polymorphic ASIC combining the flexibility of a programmable solution with the execution speed of an ASIC. In REDEFINE Compute Elements are arranged in an 8x8 grid connected via a Network on Chip (NoC) called RECONNECT, to realize the various macrofunctional blocks of an equivalent ASIC. For a 1024-FFT we carry out an application-architecture design space exploration by examining the various characterizations of Compute Elements in terms of the size of the instruction store. We further study the impact by using application specific, vectorized FUs. By setting up different partitions of the FFT algorithm for persistent execution on REDEFINE-v2, we derive the benefits of setting up pipelined execution for higher performance. The impact of the REDEFINE-v2 micro-architecture for any arbitrary N-point FFT (N > 4096) FFT is also analyzed. We report the various algorithm-architecture tradeoffs in terms of area and execution speed with that of an ASIC implementation. In addition we compare the performance gain with respect to a GPP.

The June 2010 Nicobar Earthquake: Fault Reactivation on the Subducting Oceanic Plate

The similar to 1300-km-long rupture zone of the 2004 Andaman-Sumatra megathrust earthquake continues to generate a mix of thrust, normal, and strike-slip faulting events. The 12 June 2010 M(w) 7.5 event on the subducting plate is the most recent large earthquake on the Nicobar segment. The left-lateral faulting mechanism of this event is unusual for the outer-rise region, considering the stress transfer processes that follow great underthrusting earthquakes. Another earthquake (M(w) 7.2) with a similar mechanism occurred very close to this event on 24 July 2005. These earthquakes and most of their aftershocks on the subducting plate were generated by left-lateral strike-slip faulting on north-northeast-south-southwest oriented near-vertical faults, in response to north-northwest-south-southeast directed compression. Pre-2004 earthquake faulting mechanisms on the subducting oceanic plate are consistent with this pattern. Post-2004, left-lateral faulting on the subducting oceanic plate clusters between 5 degrees N and 9 degrees N, where the 90 degrees E ridge impinges the trench axis. Our study observes that the subducting plate off the Sumatra and Nicobar segments behaves similarly to a chip of the India-Australia plate, deforming in response to a generally northwest-southeast oriented compression, an aspect that must be factored into the plate deformation models.

Energy-efficient redundant execution for chip multiprocessors

Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper, we describe a power-efficient architecture for redundant execution on chip multiprocessors (CMPs) which when coupled with our per-core dynamic voltage and frequency scaling (DVFS) algorithm significantly reduces the energy overhead of redundant execution without sacrificing performance. Our evaluation shows that this architecture has a performance overhead of only 0.3% and consumes only 1.48 times the energy of a non-fault-tolerant baseline.

Microstructure and compression behavior of chip consolidated magnesium

Chips produced by turning a commercial purity magnesium billet were cold compacted and then hot extruded at four different temperatures: 250, 300, 350, and 400 degrees C. Cast billets, of identical composition, were also extruded as reference material. Chip boundaries, visible even after 49: 1 extrusion at 400 degrees C, were observed to suppress grain coarsening. Although 250 degrees C extruded chip-consolidated product showed early onset of yielding and lower ductility, fully dense material (extruded at 400 degrees C) had nearly 40% reduction in grain size with 22% higher yield strength and comparable ductility as that of the reference. The study highlights the role of densification and grain refinement on the compression behavior of chip consolidated specimens.

Applying Genetic Algorithms to Optimize Power in Tiled SNUCA Chip Multicore Architectures

We propose a novel technique for reducing the power consumed by the on-chip cache in SNUCA chip multicore platform. This is achieved by what we call a "remap table", which maps accesses to the cache banks that are as close as possible to the cores, on which the processes are scheduled. With this technique, instead of using all the available cache, we use a portion of the cache and allocate lesser cache to the application. We formulate the problem as an energy-delay (ED) minimization problem and solve it offline using a scalable genetic algorithm approach. Our experiments show up to 40% of savings in the memory sub-system power consumption and 47% savings in energy-delay product (ED).

Applying Genetic Algorithms to Optimize Power in Tiled SNUCA Chip Multicore Architectures

We propose a novel technique for reducing the power consumed by the on-chip cache in SNUCA chip multicore platform. This is achieved by what we call a "remap table", which maps accesses to the cache banks that are as close as possible to the cores, on which the processes are scheduled. With this technique, instead of using all the available cache, we use a portion of the cache and allocate lesser cache to the application. We formulate the problem as an energy-delay (ED) minimization problem and solve it offline using a scalable genetic algorithm approach. Our experiments show up to 40% of savings in the memory sub-system power consumption and 47% savings in energy-delay product (ED).

Process control of cantilever deflection for sensor application based on optical waveguides

This paper reports on the fabrication of cantilever silicon-on-insulator (SOI) optical waveguides and presents solutions to the challenges of using a very thin 260-nm active silicon layer in the SOI structure to enable single-transverse-mode operation of the waveguide with minimal optical transmission losses. In particular, to ameliorate the anchor effect caused by the mean stress difference between the active silicon layer and buried oxide layer, a cantilever flattening process based on Ar plasma treatment is developed and presented. Vertical deflections of 0.5 mu m for 70-mu m-long cantilevers are mitigated to within few nanometers. Experimental investigations of cantilever mechanical resonance characteristics confirm the absence of significant detrimental side effects. Optical and mechanical modeling is extensively used to supplement experimental observations. This approach can satisfy the requirements for on-chip simultaneous readout of many integrated cantilever sensors in which the displacement or resonant frequency changes induced by analyte absorption are measured using an optical-waveguide-based division multiplexed system.

Experimental Studies on the Kinematics of Cutting in Granular Materials

Slow flow in granular materials is characterized by high solid fraction and sustained inter-particle interaction. The kinematics of trawling or cutting is encountered in processes such as locomotion of organisms in sand; trawl gear movement on a soil deposit; plow movement; movement of rovers, earth moving equipment etc. Additionally, this configuration is very akin to shallow drilling configuration encountered in the mining and petroleum industries. An experimental study has been made in order to understand velocity and deformation fields in cutting of a model rounded sand. Under nominal plane strain conditions, sand is subjected to orthogonal cutting at different tool-rake angles. High-resolution optical images of the region of cutting were obtained during the flow of the granular ensemble around the tool. Interesting kinematics underlying the formation of a chip and the evolution of the deformation field is seen in these experiments. These images are also analyzed using a PIV algorithm and detailed information of the deformation parameters such as velocity, strain rate and volume change is obtained.

Toward a Scalable Working Set Size Estimation Method and Its Application for Chip Multiprocessors

It is essential to accurately estimate the working set size (WSS) of an application for various optimizations such as to partition cache among virtual machines or reduce leakage power dissipated in an over-allocated cache by switching it OFF. However, the state-of-the-art heuristics such as average memory access latency (AMAL) or cache miss ratio (CMR) are poorly correlated to the WSS of an application due to 1) over-sized caches and 2) their dispersed nature. Past studies focus on estimating WSS of an application executing on a uniprocessor platform. Estimating the same for a chip multiprocessor (CMP) with a large dispersed cache is challenging due to the presence of concurrently executing threads/processes. Hence, we propose a scalable, highly accurate method to estimate WSS of an application. We call this method ``tagged WSS (TWSS)'' estimation method. We demonstrate the use of TWSS to switch-OFF the over-allocated cache ways in Static and Dynamic NonUniform Cache Architectures (SNUCA, DNUCA) on a tiled CMP. In our implementation of adaptable way SNUCA and DNUCA caches, decision of altering associativity is taken by each L2 controller. Hence, this approach scales better with the number of cores present on a CMP. It gives overall (geometric mean) 26% and 19% higher energy-delay product savings compared to AMAL and CMR heuristics on SNUCA, respectively.