Neural network modeling of associative memory: Beyond the Hopfield model

A number of neural network models, in which fixed-point and limit-cycle attractors of the underlying dynamics are used to store and associatively recall information, are described. In the first class of models, a hierarchical structure is used to store an exponentially large number of strongly correlated memories. The second class of models uses limit cycles to store and retrieve individual memories. A neurobiologically plausible network that generates low-amplitude periodic variations of activity, similar to the oscillations observed in electroencephalographic recordings, is also described. Results obtained from analytic and numerical studies of the properties of these networks are discussed.

A Comparative Study of Electrical Switching Behavior of Certain Tellurium based Chalcogenide Thin Films for Phase Change Memory (PCM) Applications

This work describes the electrical switching behavior of three telluride based amorphous chalcogenide thin film samples, Al-Te, Ge-Se-Te and Ge-Te-Si. These amorphous thin films are made using bulk glassy ingots, prepared by conventional melt quenching technique, using flash evaporation technique; while Al-Te sample has been coated in coplanar electrode geometry, Ge-Se-Te and Ge-Te-Si samples have been deposited with sandwich electrodes. It is observed that all the three samples studied, exhibit memory switching behavior in thin film form, with Ge-Te-Si sample exhibiting a faster switching characteristic. The difference seen in the switching voltages of the three samples studied has been understood on the basis of difference in device geometry and thickness. Scanning electron microscopic image of switched region of a representative Ge15Te81Si4 sample shows a structural change and formation of crystallites in the electrode region, which is responsible for making a conducting channel between the two electrodes during switching.

WOMM: A Weak Operational Memory Model

Memory models of shared memory concurrent programs define the values a read of a shared memory location is allowed to see. Such memory models are typically weaker than the intuitive sequential consistency semantics to allow efficient execution. In this paper, we present WOMM (abbreviation for Weak Operational Memory Model) that formally unifies two sources of weak behavior in hardware memory models: reordering of instructions and weakly consistent memory. We show that a large number of optimizations are allowed by WOMM. We also show that WOMM is weaker than a number of hardware memory models. Consequently, if a program behaves correctly under WOMM, it will be correct with respect to those hardware memory models. Hence, WOMM can be used as a formally specified abstraction of the hardware memory models. Moreover; unlike most weak memory models, WOMM is described using operational semantics, making it easy to integrate into a model checker for concurrent programs. We further show that WOMM has an important property - it has sequential consistency semantics for datarace-free programs.

Low electric field, easily reversible electrical set and reset processes in a Ge15Te83Si2 glass for phase change memory applications

We report here an easily reversible set-reset process in a new Ge15Te83Si2 glass that could be a promising candidate for phase change random access memory applications. The I-V characteristics of the studied sample show a comparatively low threshold electric field (E-th) of 7.3 kV/cm. Distinct differences in the type of switching behavior are achieved by means of controlling the on state current. It enables the observation of a threshold type for less than 0.7 mA beyond memory type (set) switching. The set and reset processes have been achieved with a similar magnitude of 1 mA, and with a triangular current pulse for the set process and a short duration rectangular pulse of 10 msec width for the reset operation. Further, a self-resetting effect is seen in this material upon excitation with a saw-tooth/square pulse, and their response of leading and trailing edges are discussed. About 6.5 x 10(4) set-reset cycles have been undertaken without any damage to the device. (C) 2011 American Institute of Physics. doi: 10.1063/1.3574659]

Hierarchical Directory-Based Shared Memory Architecture

We describe the design of a directory-based shared memory architecture on a hierarchical network of hypercubes. The distributed directory scheme comprises two separate hierarchical networks for handling cache requests and transfers. Further, the scheme assumes a single address space and each processing element views the entire network as contiguous memory space. The size of individual directories stored at each node of the network remains constant throughout the network. Although the size of the directory increases with the network size, the architecture is scalable. The results of the analytical studies demonstrate superior performance characteristics of our scheme compared with those of other schemes.

On the problem of spurious patterns in neural associative memory models

The problem of spurious patterns in neural associative memory models is discussed, Some suggestions to solve this problem from the literature are reviewed and their inadequacies are pointed out, A solution based on the notion of neural self-interaction with a suitably chosen magnitude is presented for the Hebb learning rule. For an optimal learning rule based on linear programming, asymmetric dilution of synaptic connections is presented as another solution to the problem of spurious patterns, With varying percentages of asymmetric dilution it is demonstrated numerically that this optimal learning rule leads to near total suppression of spurious patterns. For practical usage of neural associative memory networks a combination of the two solutions with the optimal learning rule is recommended to be the best proposition.

Network Error Correction for Unit-Delay, Memory-Free Networks Using Convolutional Codes

A single source network is said to be memory-free if all of the internal nodes (those except the source and the sinks) do not employ memory but merely send linear combinations of the symbols received at their incoming edges on their outgoing edges. In this work, we introduce network-error correction for single source, acyclic, unit-delay, memory-free networks with coherent network coding for multicast. A convolutional code is designed at the source based on the network code in order to correct network- errors that correspond to any of a given set of error patterns, as long as consecutive errors are separated by a certain interval which depends on the convolutional code selected. Bounds on this interval and the field size required for constructing the convolutional code with the required free distance are also obtained. We illustrate the performance of convolutional network error correcting codes (CNECCs) designed for the unit-delay networks using simulations of CNECCs on an example network under a probabilistic error model.

Glassy behavior in neural network models of associative memory

Neural network models of associative memory exhibit a large number of spurious attractors of the network dynamics which are not correlated with any memory state. These spurious attractors, analogous to "glassy" local minima of the energy or free energy of a system of particles, degrade the performance of the network by trapping trajectories starting from states that are not close to one of the memory states. Different methods for reducing the adverse effects of spurious attractors are examined with emphasis on the role of synaptic asymmetry. (C) 2002 Elsevier Science B.V. All rights reserved.

Study of thickness dependence on electrical properties of (Pb,La)TiO3 thin films for memory applications

Lead-lanthanum-titanate (Pb0.72La0.28)TiO3 (PLT) is one of the interesting materials for DRAM applications due to its room temperature paraelectric nature and its higher dielectric permittivity. PLT thin films of different thickness ranging from 0.54- 0.9 mum were deposited on Pt coated Si substrates by excimer laser ablation technique. We have measured the voltage (field) dependence, the thickness dependence, temperature dependence of dc leakage currents and analysis is done on these PLT thin films. Current- voltage characteristics were measured at different temperatures for different thick films and the thickness dependence of leakage current has been explained by considering space charge limited conduction mechanism. The charge transport phenomena were studied in detail for films of different thicknesses for dynamic random access memory applications.

Composition tunable memory and threshold switching in Al20As xTe80− x semiconducting glasses

I-V studies indicate a composition dependent switching behavior (Memory or Threshold) in bulk Al20AsxTe80−x glasses, which is determined by the coordination and composition of aluminum. Investigations on temperature and thickness dependence of switching and structural studies on switched samples suggest thermal and electronic mechanisms of switching for the memory and threshold samples, respectively. The present results also show that these samples have a wider composition range of threshold behavior with lower threshold voltages compared to other threshold samples.

Design and Implementation of a Flexible and Memory Efficient Operating System for Sensor Nodes

Sensor network nodes exhibit characteristics of both embedded systems and general-purpose systems.A sensor network operating system is a kind of embedded operating system, but unlike a typical embedded operating system, sensor network operatin g system may not be real time, and is constrained by memory and energy constraints. Most sensor network operating systems are based on event-driven approach. Event-driven approach is efficient in terms of time and space.Also this approach does not require a separate stack for each execution context. But using this model, it is difficult to implement long running tasks, like cryptographic operations. A thread based computation requires a separate stack for each execution context, and is less efficient in terms of time and space. In this paper, we propose a thread based execution model that uses only a fixed number of stacks. In this execution model, the number of stacks at each priority level are fixed. It minimizes the stack requirement for multi-threading environment and at the same time provides ease of programming. We give an implementation of this model in Contiki OS by separating thread implementation from protothread implementation completely. We have tested our OS by implementing a clock synchronization protocol using it.

Micro stepping of Shape Memory Alloy based Poly Phase motor

In literature we find broadly two types of shape memory alloy based motors namely limited rotation motor and unlimited rotation motor. The unlimited rotation type SMA based motor reported in literature uses SMA springs for actuation. An attempt has been made in this paper to develop an unlimited rotation type balanced poly phase motor based on SMA wire in series with a spring in each phase. By isolating SMA actuation and spring action we are able achieve a constant force by the SMA wire through out its range of operation. The Poly phase motor can be used in stepping mode for generating incremental motion and servo mode for generating continuous motion. A method of achieving servo motion by micro stepping is presented. Micro stepping consists of controlling single-phase temperature with a position feedback. The motor has been modeled with a new approach to the SMA wire Hysterysis model. Motor is simulated for different responses and the results are compared with the experimental data.

Java Memory Model aware Software validation

The Java Memory Model (JMM) provides a semantics of Java multithreading for any implementation platform. The JMM is defined in a declarative fashion with an allowed program execution being defined in terms of existence of "commit sequences" (roughly, the order in which actions in the execution are committed). In this work, we develop OpMM, an operational under-approximation of the JMM. The immediate motivation of this work lies in integrating a formal specification of the JMM with software model checkers. We show how our operational memory model description can be integrated into a Java Path Finder (JPF) style model checker for Java programs.

Memory Architecture Exploration Framework for Cache Based Embedded SoC

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences critical system design objectives like area, power and performance. Hence the embedded system designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.