Porous Flower-like alpha-Fe2O3 Nanostructure: A High Performance Anode Material for Lithium-ion Batteries

Porous flower-like alpha-Fe2O3 nanostructures have been synthesized by ethylene glycol mediated iron alkoxide as an intermediate and studied as an anode material of Li-ion battery. The iron alkoxide precursor is heated at different temperatures from 300 to 700 degrees C. The alpha-Fe2O3 samples possess porosity and high surface area. There is a decrease in pore volume as well as surface area by increasing the preparation temperature. The reversible cycling properties of the alpha-Fe2O3 nanostructures have been evaluated by cyclic voltammetry, galvanostatic charge discharge cycling, and galvanostatic intermittent titration measurements at ambient temperature. The initial discharge capacity values of 1063, 1168,1183, 1152 and 968 mAh g(-1) at a specific current of 50 mA g(-1) are obtained for the samples prepared at 300, 400, 500, 600 and 700 degrees C, respectively. The samples prepared at 500 and 600 degrees C exhibit good cycling performance with high rate capability. The high rate capacity is attributed to porous nature of the materials. As the iron oxides are inexpensive and environmental friendly, the alpha-Fe2O3 has potential application as anode material for rechargeable Li batteries. (C) 2015 Elsevier Ltd. All rights reserved.

Few-layer graphene/ZnO nanowires based high performance UV photodetector

A graphene and zinc oxide nanowires (G/ZnO NWs) based ultraviolet (UV) photodetector presents excellent responsivity and photocurrent gain with detectivity. Graphene due to higher charge carrier transport mobility induces faster response to UV illumination at the interface between ZnO and graphene with improved response and decay times as compared to a ZnO NWs device alone. A linear increase is revealed for both the responsivity and photocurrent gain of the G/ZnO NWs device with the applied bias. These results suggest that the G/ZnO NWs device exhibits great promise for highly efficient UV photodetectors.

High-Performance Stacked TiO2-ZrO2 and Si-doped ZrO2 Metal-Insulator-Metal Capacitors

Metal-insulator-metal (MIM) capacitors for DRAM applications have been realised using stacked TiO2-ZrO2 (TiO2/ZrO2 and ZrO2/TiO2) and Si-doped ZrO2 (TiO2/Si-doped ZrO2) dielectrics. High capacitance densities (> 42 fF/mu m(2)), low leakage current densities (< 5 x 10(-7) A/cm(2) at -1 V), and sub-nm EOT (< 0.8 nm) have been achieved. The effects of constant voltage stress on the device characteristics is studied. The structural analysis of the samples is performed by X-ray diffraction measurements, and this is correlated to the electrical characteristics of the devices. The surface chemical states of the films are analyzed through X-ray photoelectron spectroscopy measurements. The doped-dielectric stack (TiO2/Si-doped ZrO2) helps to reduce leakage current density and improve reliability, with a marginal reduction in capacitance density; compared to their undoped counterparts (TiO2/ZrO2 and ZrO2/TiO2). We compare the device performance of the fabricated capacitors with other stacked high-k MIM capacitors reported in recent literature.

High-Performance Sensors Based on Resistance Fluctuations of Single-Layer-Graphene Transistors

One of the most interesting predicted applications of graphenemonolayer-based devices is as high-quality sensors. In this article, we show, through systematic experiments, a chemical vapor sensor based on the measurement of lowfrequency resistance fluctuations of single-layer-graphene field-effect-transistor devices. The sensor has extremely high sensitivity, very high specificity, high fidelity, and fast response times. The performance of the device using this scheme of measurement (which uses resistance fluctuations as the detection parameter) is more than 2 orders of magnitude better than a detection scheme in which changes in the average value of the resistance is monitored. We propose a number-densityfluctuation-based model to explain the superior characteristics of a noisemeasurement-based detection scheme presented in this article.

High performance sol-gel spin-coated titanium dioxide dielectric based MOS structures

High-kappa TiO2 thin films have been fabricated using cost effective sol-gel and spin-coating technique on p-Si (100) wafer. Plasma activation process was used for better adhesion between TiO2 films and Si. The influence of annealing temperature on the structure-electrical properties of titania films were investigated in detail. Both XRD and Raman studies indicate that the anatase phase crystallizes at 400 degrees C, retaining its structural integrity up to 1000 degrees C. The thickness of the deposited films did not vary significantly with the annealing temperature, although the refractive index and the RMS roughness enhanced considerably, accompanied by a decrease in porosity. For electrical measurements, the films were integrated in metal-oxide-semiconductor (MOS) structure. The electrical measurements evoke a temperature dependent dielectric constant with low leakage current density. The Capacitance-voltage (C-V) characteristics of the films annealed at 400 degrees C exhibited a high value of dielectric constant (similar to 34). Further, frequency dependent C-V measurements showed a huge dispersion in accumulation capacitance due to the presence of TiO2/Si interface states and dielectric polarization, was found to follow power law dependence on frequency (with exponent `s'=0.85). A low leakage current density of 3.6 x 10(-7) A/cm(2) at 1 V was observed for the films annealed at 600 degrees C. The results of structure-electrical properties suggest that the deposition of titania by wet chemical method is more attractive and cost-effective for production of high-kappa materials compared to other advanced deposition techniques such as sputtering, MBE, MOCVD and AID. The results also suggest that the high value of dielectric constant kappa obtained at low processing temperature expands its scope as a potential dielectric layer in MOS device technology. (C) 2015 Elsevier Ltd. All rights reserved.

High Performance Modulation of High-Frequency AC Link Inverter

Inverters with high voltage conversion ratio are used in systems with sources such as batteries, photovoltaic (PV) modules or fuel cells. Transformers are often used in such inverters to provide the required voltage conversion ratio and isolation. In this paper, a compact high-frequency (HF) transformer interfaced AC link inverter with lossless snubber is discussed. A high performance synchronized modulation scheme is proposed for this inverter. This modulation addresses the issue of over-voltage spikes due to transformer leakage inductance and it is shown that the circuit can operate safely even when the turn-on delay, such as dead-time, is not used in the HF rectifier section. The problem of spurious turn-on in the HF inverter switches is also mitigated by the proposed modulation method. The circuit performance is validated experimentally with a $900W$ prototype inverter.

Critical investigation of high performance spin-coated high-kappa titania thin films based MOS capacitor

We report the tunable dielectric constant of titania films with low leakage current density. Titanium dioxide (TiO2) films of three different thicknesses (36, 63 and 91 nm) were deposited by the consecutive steps of solution preparation, spin-coating, drying, and firing at different temperatures. The problem of poor adhesion between Si substrate and TiO2 insulating layer was resolved by using the plasma activation process. The surface roughness was found to increase with increasing thickness and annealing temperature. The electrical investigation was carried out using metal-oxide-semiconductor structure. The flat band voltage (V-FB), oxide trapped charge (Q(ot)), dielectric constant (kappa) and equivalent oxide thicknesses are calculated from capacitance-voltage (C-V) curves. The C-V characteristics indicate a thickness dependent dielectric constant. The dielectric constant increases from 31 to 78 as thickness increases from 36 to 91 nm. In addition to that the dielectric constant was found to be annealing temperature and frequency dependent. The films having thickness 91 nm and annealed at 600 A degrees C shows the low leakage current density. Our study provides a broad insight of the processing parameters towards the use of titania as high-kappa insulating layer, which might be useful in Si and polymer based flexible devices.

A finite element assessment of flexural strength of prestressed concrete beams with fiber reinforcement

This paper presents an assessment of the flexural behavior of 15 fully/partially prestressed high strength concrete beams containing steel fibers investigated using three-dimensional nonlinear finite elemental analysis. The experimental results consisted of eight fully and seven partially prestressed beams, which were designed to be flexure dominant in the absence of fibers. The main parameters varied in the tests were: the levels of prestressing force (i.e, in partially prestressed beams 50% of the prestress was reduced with the introduction of two high strength deformed bars instead), fiber volume fractions (0%, 0.5%, 1.0% and 1.5%), fiber location (full depth and partial depth over full length and half the depth over the shear span only). A three-dimensional nonlinear finite element analysis was conducted using ANSYS 5.5 [Theory Reference Manual. In: Kohnke P, editor. Elements Reference Manual. 8th ed. September 1998] general purpose finite element software to study the flexural behavior of both fully and partially prestressed fiber reinforced concrete beams. Influence of fibers on the concrete failure surface and stress-strain response of high strength concrete and the nonlinear stress-strain curves of prestressing wire and deformed bar were considered in the present analysis. In the finite element model. tension stiffening and bond slip between concrete and reinforcement (fibers., prestressing wire, and conventional reinforcing steel bar) have also been considered explicitly. The fraction of the entire volume of the fiber present along the longitudinal axis of the prestressed beams alone has been modeled explicitly as it is expected that these fibers would contribute to the mobilization of forces required to sustain the applied loads across the crack interfaces through their bridging action. A comparison of results from both tests and analysis on all 15 specimens confirm that, inclusion of fibers over a partial depth in the tensile side of the prestressed flexural structural members was economical and led to considerable cost saving without sacrificing on the desired performance. However. beams having fibers over half the depth in only the shear span, did not show any increase in the ultimate load or deformational characteristics when compared to plain concrete beams. (C) 2002 Published by Elsevier Science Ltd.

A Scalable High Throughput Firewall in FPGA

High end network security applications demand high speed operation and large rule set support. Packet classification is the core functionality that demands high throughput in such applications. This paper proposes a packet classification architecture to meet such high throughput. We have implemented a Firewall with this architecture in reconflgurable hardware. We propose an extension to Distributed Crossproducting of Field Labels (DCFL) technique to achieve scalable and high performance architecture. The implemented Firewall takes advantage of inherent structure and redundancy of rule set by using our DCFL Extended (DCFLE) algorithm. The use of DCFLE algorithm results in both speed and area improvement when it is implemented in hardware. Although we restrict ourselves to standard 5-tuple matching, the architecture supports additional fields. High throughput classification invariably uses Ternary Content Addressable Memory (TCAM) for prefix matching, though TCAM fares poorly in terms of area and power efficiency. Use of TCAM for port range matching is expensive, as the range to prefix conversion results in large number of prefixes leading to storage inefficiency. Extended TCAM (ETCAM) is fast and the most storage efficient solution for range matching. We present for the first time a reconfigurable hardware implementation of ETCAM. We have implemented our Firewall as an embedded system on Virtex-II Pro FPGA based platform, running Linux with the packet classification in hardware. The Firewall was tested in real time with 1 Gbps Ethernet link and 128 sample rules. The packet classification hardware uses a quarter of logic resources and slightly over one third of memory resources of XC2VP30 FPGA. It achieves a maximum classification throughput of 50 million packet/s corresponding to 16 Gbps link rate for the worst case packet size. The Firewall rule update involves only memory re-initialization in software without any hardware change.

A Scalable High Throughput Firewall in FPGA

High end network security applications demand high speed operation and large rule set support. Packet classification is the core functionality that demands high throughput in such applications. This paper proposes a packet classification architecture to meet such high throughput. We have Implemented a Firewall with this architecture in reconfigurable hardware. We propose an extension to Distributed Crossproducting of Field Labels (DCFL) technique to achieve scalable and high performance architecture. The implemented Firewall takes advantage of inherent structure and redundancy of rule set by using, our DCFL Extended (DCFLE) algorithm. The use of DCFLE algorithm results In both speed and area Improvement when It is Implemented in hardware. Although we restrict ourselves to standard 5-tuple matching, the architecture supports additional fields.High throughput classification Invariably uses Ternary Content Addressable Memory (TCAM) for prefix matching, though TCAM fares poorly In terms of area and power efficiency. Use of TCAM for port range matching is expensive, as the range to prefix conversion results in large number of prefixes leading to storage inefficiency. Extended TCAM (ETCAM) is fast and the most storage efficient solution for range matching. We present for the first time a reconfigurable hardware Implementation of ETCAM. We have implemented our Firewall as an embedded system on Virtex-II Pro FPGA based platform, running Linux with the packet classification in hardware. The Firewall was tested in real time with 1 Gbps Ethernet link and 128 sample rules. The packet classification hardware uses a quarter of logic resources and slightly over one third of memory resources of XC2VP30 FPGA. It achieves a maximum classification throughput of 50 million packet/s corresponding to 16 Gbps link rate for file worst case packet size. The Firewall rule update Involves only memory re-initialiization in software without any hardware change.

Nonlinear transport in semiconducting polymers at high carrier densities

Conducting and semiconducting polymers are important materials in the development of printed, flexible, large-area electronics such as flat-panel displays and photovoltaic cells. There has been rapid progress in developing conjugated polymers with high transport mobility required for high-performance field-effect transistors (FETs), beginning(1) with mobilities around 10(-4) cm(2) V-1 s(-1) to a recent report(2) of 1 cm(2) V-1 s(-1) for poly(2,5-bis(3-tetradecylthiophen-2-yl) thieno[3,2-b] thiophene) (PBTTT). Here, the electrical properties of PBTTT are studied at high charge densities both as the semiconductor layer in FETs and in electrochemically doped films to determine the transport mechanism. We show that data obtained using a wide range of parameters (temperature, gate-induced carrier density, source-drain voltage and doping level) scale onto the universal curve predicted for transport in the Luttinger liquid description of the one-dimensional `metal'.

Exploring energy-performance trade-offs for heterogeneous interconnect clustered VLIW processors

Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving clock speed, reducing energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. This communication happens over long global wires which leads to delay in execution and significantly high energy consumption.In this paper, we propose a new instruction scheduling algorithm that exploits scheduling slacks of instructions and communication slacks of data values together to achieve better energy-performance trade-offs for clustered architectures with heterogeneous interconnect. Our instruction scheduling algorithm achieves 35% and 40% reduction in communication energy, whereas the overall energy-delay product improves by 4.5% and 6.5% respectively for 2 cluster and 4 cluster machines with marginal increase (1.6% and 1.1%) in execution time. Our test bed uses the Trimaran compiler infrastructure.

Construction and use of linear regression models for processor performance analysis

Processor architects have a challenging task of evaluating a large design space consisting of several interacting parameters and optimizations. In order to assist architects in making crucial design decisions, we build linear regression models that relate Processor performance to micro-architecture parameters, using simulation based experiments. We obtain good approximate models using an iterative process in which Akaike's information criteria is used to extract a good linear model from a small set of simulations, and limited further simulation is guided by the model using D-optimal experimental designs. The iterative process is repeated until desired error bounds are achieved. We used this procedure to establish the relationship of the CPI performance response to 26 key micro-architectural parameters using a detailed cycle-by-cycle superscalar processor simulator The resulting models provide a significance ordering on all micro-architectural parameters and their interactions, and explain the performance variations of micro-architectural techniques.

Improving Performance of Result Caches in Network Processors

Digest caches have been proposed as an effective method tospeed up packet classification in network processors. In this paper, weshow that the presence of a large number of small flows and a few largeflows in the Internet has an adverse impact on the performance of thesedigest caches. In the Internet, a few large flows transfer a majority ofthe packets whereas the contribution of several small flows to the totalnumber of packets transferred is small. In such a scenario, the LRUcache replacement policy, which gives maximum priority to the mostrecently accessed digest, tends to evict digests belonging to the few largeflows. We propose a new cache management algorithm called SaturatingPriority (SP) which aims at improving the performance of digest cachesin network processors by exploiting the disparity between the number offlows and the number of packets transferred. Our experimental resultsdemonstrate that SP performs better than the widely used LRU cachereplacement policy in size constrained caches. Further, we characterizethe misses experienced by flow identifiers in digest caches.

Adaptive Filtering Technique and DSP Based Implementation for High-Speed Distance Protection

The paper presents an adaptive Fourier filtering technique and a relaying scheme based on a combination of a digital band-pass filter along with a three-sample algorithm, for applications in high-speed numerical distance protection. To enhance the performance of above-mentioned technique, a high-speed fault detector has been used. MATLAB based simulation studies show that the adaptive Fourier filtering technique provides fast tripping for near faults and security for farther faults. The digital relaying scheme based on a combination of digital band-pass filter along with three-sample data window algorithm also provides accurate and high-speed detection of faults. The paper also proposes a high performance 16-bit fixed point DSP (Texas Instruments TMS320LF2407A) processor based hardware scheme suitable for implementation of the above techniques. To evaluate the performance of the proposed relaying scheme under steady state and transient conditions, PC based menu driven relay test procedures are developed using National Instruments LabVIEW software. The test signals are generated in real time using LabVIEW compatible analog output modules. The results obtained from the simulation studies as well as hardware implementations are also presented.