53 resultados para Field-Programmable Gate Array (FPGA)


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In this work a physically based analytical quantum threshold voltage model for the triple gate long channel metal oxide semiconductor field effect transistor is developed The proposed model is based on the analytical solution of two-dimensional Poisson and two-dimensional Schrodinger equation Proposed model is extended for short channel devices by including semi-empirical correction The impact of effective mass variation with film thicknesses is also discussed using the proposed model All models are fully validated against the professional numerical device simulator for a wide range of device geometries (C) 2010 Elsevier Ltd All rights reserved

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In this paper, we propose a novel S/D engineering for dual-gated Bilayer Graphene (BLG) Field Effect Transistor (FET) using doped semiconductors (with a bandgap) as source and drain to obtain unipolar complementary transistors. To simulate the device, a self-consistent Non-Equilibrium Green's Function (NEGF) solver has been developed and validated against published experimental data. Using the simulator, we predict an on-off ratio in excess of 10(4) and a subthreshold slope of similar to 110mV/decade with excellent scalability and current saturation, for a 20nm gate length unipolar BLG FET. However, the performance of the proposed device is found to be strongly dependent on the S/D series resistance effect. The obtained results show significant improvements over existing reports, marking an important step towards bilayer graphene logic devices.

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A new range of programmable logic devices are revolutionizing the way complex digital hardware is designed and built all over the world. Being able to test these devices in order to validate and dynamically improve on the design is crucial. This paper describes a low-cost FPGA tester that can test SRAM based FPGAs in the laboratory.

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It has been observed experimentally that the collective field emission from an array of Carbon Nanotubes (CNTs) exhibits fluctuation and degradation, and produces thermal spikes, resulting in electro-mechanical fatigue and failure of CNTs. Based on a new coupled multiphysics model incorporating the electron-phonon transport and thermo-electrically activated breakdown, a novel method for estimating accurately the lifetime of CNT arrays has been developed in this paper. The main results are discussed for CNT arrays during the field emission process. It is shown that the time-to-failure of CNT arrays increases with the decrease in the angle of tip orientation. This observation has important ramifications for such areas as biomedical X-ray devices using patterned films of CNTs.

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Experimental realization of quantum information processing in the field of nuclear magnetic resonance (NMR) has been well established. Implementation of conditional phase-shift gate has been a significant step, which has lead to realization of important algorithms such as Grover's search algorithm and quantum Fourier transform. This gate has so far been implemented in NMR by using coupling evolution method. We demonstrate here the implementation of the conditional phase-shift gate using transition selective pulses. As an application of the gate, we demonstrate Grover's search algorithm and quantum Fourier transform by simulations and experiments using transition selective pulses. (C) 2002 Elsevier Science (USA). All rights reserved.

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The conventional metal oxide semiconductor field effect transistor (MOSFET)may not be suitable for future low standby power (LSTP) applications due to its high off-state current as the sub-threshold swing is theoretically limited to 60mV/decade. Tunnel field effect transistor (TFET) based on gate controlled band to band tunneling has attracted attention for such applications due to its extremely small sub-threshold swing (much less than 60mV/decade). This paper takes a simulation approach to gain some insight into its electrostatics and the carrier transport mechanism. Using 2D device simulations, a thorough study and analysis of the electrical parameters of the planar double gate TFET is performed. Due to excellent sub-threshold characteristics and a reverse biased structure, it offers orders of magnitude less leakage current compared to the conventional MOSFET. In this work, it is shown that the device can be scaled down to channel lengths as small as 30 nm without affecting its performance. Also, it is observed that the bulk region of the device plays a major role in determining the sub-threshold characteristics of the device and considerable improvement in performance (in terms of ION/IOFF ratio) can be achieved if the thickness of the device is reduced. An ION/IOFF ratio of 2x1012 and a minimum point sub-threshold swing of 22mV/decade is obtained.

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The main idea proposed in this paper is that in a vertically aligned array of short carbon nanotubes (CNTs) grown on a metal substrate, we consider a frequency dependent electric field, so that the mode-specific propagation of phonons, in correspondence with the strained band structure and the dispersion curves, take place. We perform theoretical calculations to validate this idea with a view of optimizing the field emission behavior of the CNT array. This is the first approach of its kind, and is in contrast to the the conventional approach where a DC bias voltage is applied in order to observe field emission. A first set of experimental results presented in this paper gives a clear indication that phonon-assisted control of field emission current in CNT based thin film diode is possible.

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We present low-temperature electrical transport experiments in five field-effect transistor devices consisting of monolayer, bilayer, and trilayer MoS(2) films, mechanically exfoliated onto Si/SiO(2) substrate. Our experiments reveal that the electronic states In all films are localized well up to room temperature over the experimentally accessible range of gate voltage. This manifests in two-dimensional (2D) variable range hopping (VRH) at high temperatures, while below similar to 30 K, the conductivity displays oscillatory structures In gate voltage arising from resonant tunneling at the localized sites. From the correlation energy (T(0)) of VRH and gate voltage dependence of conductivity, we suggest that Coulomb potential from trapped charges In the substrate is the dominant source of disorder in MoS(2) field-effect devices, which leads to carrier localization, as well.

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The performance characteristics of a junction field-effect transistor (j.f.e.t.) are evaluated considering the presence of the gap between the gate electrode and the source and drain terminals. It is concluded that the effect of the gap is to demand a higher drain voltage to maintain the same drain current. So long as the device is operated at the same drain current, the presence of the gap does not change the performance of the device as an amplifier. The nature of the performance of the device as a variable resistor is not affected by the gap if it is less than or equal to the physical height of the channel. For gap lengths larger than the channel height, the effect of the gap is to add a series resistance in the drain.

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Surface-potential-based compact charge models for symmetric double-gate metal-oxide-semiconductor field-effect transistors (SDG-MOSFETs) are based on the fundamental assumption of having equal oxide thicknesses for both gates. However, for practical devices, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. In this paper, we propose a simple surface-potential-based charge model, which is applicable for tied double-gate MOSFETs having same gate work function but could have any difference in gate oxide thickness. The proposed model utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and thus, it could be implemented in any circuit simulator very easily and extendable to short-channel devices. We also propose a simple physics-based perturbation technique by which the surface potentials of an asymmetric device could be obtained just by solving the input voltage equation of SDG devices for small asymmetry cases. The proposed model, which shows excellent agreement with numerical and TCAD simulations, is implemented in a professional circuit simulator through the Verilog-A interface and demonstrated for a 101-stage ring oscillator simulation. It is also shown that the proposed model preserves the source/drain symmetry, which is essential for RF circuit design.

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We present an analytical field-effect method to extract the density of subgap states (subgap DOS) in amorphous semiconductor thin-film transistors (TFTs), using a closed-form relationship between surface potential and gate voltage. By accounting the interface states in the subthreshold characteristics, the subgap DOS is retrieved, leading to a reasonably accurate description of field-effect mobility and its gate voltage dependence. The method proposed here is very useful not only in extracting device performance but also in physically based compact TFT modeling for circuit simulation.

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In this work, we observe gate tunable negative differential conductance (NDC) and current saturation in single layer and bilayer graphene transistor at high source-drain field, which arise due to the interplay among (1) self-heating, (2) hot carrier injection, and (3) drain induced minority carrier injection. The magnitude of the NDC is found to be reduced for a bilayer, in agreement with its weaker carrier-optical phonon coupling and less efficient hot carrier injection. The contributions of different mechanisms to the observed results are decoupled through fast transient measurements with nanosecond resolution. The findings provide insights into high field transport in graphene. (C) 2012 American Institute of Physics. http://dx.doi.org/10.1063/1.4754103]

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A CMOS gas sensor array platform with digital read-out containing 27 sensor pixels and a reference pixel is presented. A signal conditioning circuit at each pixel includes digitally programmable gain stages for sensor signal amplification followed by a second order continuous time delta sigma modulator for digitization. Each sensor pixel can be functionalized with a distinct sensing material that facilitates transduction based on impedance change. Impedance spectrum (up to 10 KHz) of the sensor is obtained off-chip by computing the fast Fourier transform of sensor and reference pixel outputs. The reference pixel also compensates for the phase shift introduced by the signal processing circuits. The chip also contains a temperature sensor with digital readout for ambient temperature measurement. A sensor pixel is functionalized with polycarbazole conducting polymer for sensing volatile organic gases and measurement results are presented. The chip is fabricated in a 0.35 CMOS technology and requires a single step post processing for functionalization. It consumes 57 mW from a 3.3 V supply.

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We present electrical transport arid low frequency (1/f) noise measurements on mechanically exfoliated single, In and triLayer MoS2-based FPI devices on Si/SiO2 substrate. We find that tie electronic states hi MoS2 are localized at low temperatures (T) and conduction happens through variable range hopping (VRH). A steep increase of 1/f noise with decreasing T, typical for localized regime was observed in all of our devices. From gate voltage dependence of noise, we find that the noise power is inversely proportional to square of the number density (proportional to 1/n(2)) for a wide range of T, indicating number density fluctuations to be the dominant source of 1/f noise in these MoS2 FETs.

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Neural activity across the brain shows both spatial and temporal correlations at multiple scales, and understanding these correlations is a key step toward understanding cortical processing. Correlation in the local field potential (LFP) recorded from two brain areas is often characterized by computing the coherence, which is generally taken to reflect the degree of phase consistency across trials between two sites. Coherence, however, depends on two factors-phase consistency as well as amplitude covariation across trials-but the spatial structure of amplitude correlations across sites and its contribution to coherence are not well characterized. We recorded LFP from an array of microelectrodes chronically implanted in the primary visual cortex of monkeys and studied correlations in amplitude across electrodes as a function of interelectrode distance. We found that amplitude correlations showed a similar trend as coherence as a function of frequency and interelectrode distance. Importantly, even when phases were completely randomized between two electrodes, amplitude correlations introduced significant coherence. To quantify the contributions of phase consistency and amplitude correlations to coherence, we simulated pairs of sinusoids with varying phase consistency and amplitude correlations. These simulations confirmed that amplitude correlations can significantly bias coherence measurements, resulting in either over-or underestimation of true phase coherence. Our results highlight the importance of accounting for the correlations in amplitude while using coherence to study phase relationships across sites and frequencies.