A FRAMEWORK FOR THE ERROR ANALYSIS OF DISCONTINUOUS FINITE ELEMENT METHODS FOR ELLIPTIC OPTIMAL CONTROL PROBLEMS AND APPLICATIONS TO C-0 IP METHODS

In this article, an abstract framework for the error analysis of discontinuous Galerkin methods for control constrained optimal control problems is developed. The analysis establishes the best approximation result from a priori analysis point of view and delivers a reliable and efficient a posteriori error estimator. The results are applicable to a variety of problems just under the minimal regularity possessed by the well-posedness of the problem. Subsequently, the applications of C-0 interior penalty methods for a boundary control problem as well as a distributed control problem governed by the biharmonic equation subject to simply supported boundary conditions are discussed through the abstract analysis. Numerical experiments illustrate the theoretical findings.

A Scalable High Throughput Firewall in FPGA

High end network security applications demand high speed operation and large rule set support. Packet classification is the core functionality that demands high throughput in such applications. This paper proposes a packet classification architecture to meet such high throughput. We have implemented a Firewall with this architecture in reconflgurable hardware. We propose an extension to Distributed Crossproducting of Field Labels (DCFL) technique to achieve scalable and high performance architecture. The implemented Firewall takes advantage of inherent structure and redundancy of rule set by using our DCFL Extended (DCFLE) algorithm. The use of DCFLE algorithm results in both speed and area improvement when it is implemented in hardware. Although we restrict ourselves to standard 5-tuple matching, the architecture supports additional fields. High throughput classification invariably uses Ternary Content Addressable Memory (TCAM) for prefix matching, though TCAM fares poorly in terms of area and power efficiency. Use of TCAM for port range matching is expensive, as the range to prefix conversion results in large number of prefixes leading to storage inefficiency. Extended TCAM (ETCAM) is fast and the most storage efficient solution for range matching. We present for the first time a reconfigurable hardware implementation of ETCAM. We have implemented our Firewall as an embedded system on Virtex-II Pro FPGA based platform, running Linux with the packet classification in hardware. The Firewall was tested in real time with 1 Gbps Ethernet link and 128 sample rules. The packet classification hardware uses a quarter of logic resources and slightly over one third of memory resources of XC2VP30 FPGA. It achieves a maximum classification throughput of 50 million packet/s corresponding to 16 Gbps link rate for the worst case packet size. The Firewall rule update involves only memory re-initialization in software without any hardware change.

Influence of Martensite Content and Morphology on Tensile and Impact Properties of High-Martensite Dual-Phase Steels

A series of dual-phase (DP) steels containing finely dispersed martensite with different volume fractions of martensite (V-m) were produced by intermediate quenching of a boron- and vanadium-containing microalloyed steel. The volume fraction of martensite was varied from 0.3 to 0.8 by changing the intercritical annealing temperature. The tensile and impact properties of these steels were studied and compared to those of step-quenched steels, which showed banded microstructures. The experimental results show that DP steels with finely dispersed microstructures have excellent mechanical properties, including high impact toughness values, with an optimum in properties obtained at similar to 0.55 V-m. A further increase in V-m was found to decrease the yield and tensile strengths as well as the impact properties. It was shown that models developed on the basis of a rule of mixtures are inadequate in capturing the tensile properties of DP steels with V-m > 0.55. Jaoul-Crussard analyses of the work-hardening behavior of the high-martensite volume fraction DP steels show three distinct stages of plastic deformation.

A Scalable High Throughput Firewall in FPGA

High end network security applications demand high speed operation and large rule set support. Packet classification is the core functionality that demands high throughput in such applications. This paper proposes a packet classification architecture to meet such high throughput. We have Implemented a Firewall with this architecture in reconfigurable hardware. We propose an extension to Distributed Crossproducting of Field Labels (DCFL) technique to achieve scalable and high performance architecture. The implemented Firewall takes advantage of inherent structure and redundancy of rule set by using, our DCFL Extended (DCFLE) algorithm. The use of DCFLE algorithm results In both speed and area Improvement when It is Implemented in hardware. Although we restrict ourselves to standard 5-tuple matching, the architecture supports additional fields.High throughput classification Invariably uses Ternary Content Addressable Memory (TCAM) for prefix matching, though TCAM fares poorly In terms of area and power efficiency. Use of TCAM for port range matching is expensive, as the range to prefix conversion results in large number of prefixes leading to storage inefficiency. Extended TCAM (ETCAM) is fast and the most storage efficient solution for range matching. We present for the first time a reconfigurable hardware Implementation of ETCAM. We have implemented our Firewall as an embedded system on Virtex-II Pro FPGA based platform, running Linux with the packet classification in hardware. The Firewall was tested in real time with 1 Gbps Ethernet link and 128 sample rules. The packet classification hardware uses a quarter of logic resources and slightly over one third of memory resources of XC2VP30 FPGA. It achieves a maximum classification throughput of 50 million packet/s corresponding to 16 Gbps link rate for file worst case packet size. The Firewall rule update Involves only memory re-initialiization in software without any hardware change.

Synthesis of plane linkages to generate functions of two variables using point position reductionâII. Sliding inputs and outputs

The paper presents simple graphical procedures for the position synthesis of plane linkage mechanisms with sliding inputs and output to generate functions of two independent variables. The procedures are based on point position reduction and permit synthesis of the linkage to satisfy up to five arbitrarily selected precision positions.

A time minimising transportation problem with quality dependent time

The usual assumption made in time minimising transportation problem is that the time for transporting a positive amount in a route is independent of the actual amount transported in that route. In this paper we make a more general and natural assumption that the time depends on the actual amount transported. We assume that the time function for each route is an increasing piecewise constant function. Four algorithms - (1) a threshold algorithm, (2) an upper bounding technique, (3) a primal dual approach, and (4) a branch and bound algorithm - are presented to solve the given problem. A method is also given to compute the minimum bottle-neck shipment corresponding to the optimal time. A numerical example is solved illustrating the algorithms presented in this paper.

Field-Effect and Frequency Dependent Transport in Semiconductor-Enriched Single-Wall Carbon Nanotube Network Device

The electrical and optical response of a field-effect device comprising a network of semiconductor-enriched single-wall carbon nanotubes, gated with sodium chloride solution is investigated. Field-effect is demonstrated in a device that uses facile fabrication techniques along with a small-ion as the gate electrolyte-and this is accomplished as a result of the semiconductor enhancement of the tubes. The optical transparency and electrical resistance of the device are modulated with gate voltage. A time-response study of the modulation of optical transparency and electrical resistance upon application of gate voltage suggests the percolative charge transport in the network. Also the ac response in the network is investigated as a function of frequency and temperature down to 5 K. An empirical relation between onset frequency and temperature is determined.

An optimal weighted-average congestion based pricing scheme for enhanced QoS

Pricing is an effective tool to control congestion and achieve quality of service (QoS) provisioning for multiple differentiated levels of service. In this paper, we consider the problem of pricing for congestion control in the case of a network of nodes under a single service class and multiple queues, and present a multi-layered pricing scheme. We propose an algorithm for finding the optimal state dependent price levels for individual queues, at each node. The pricing policy used depends on a weighted average queue length at each node. This helps in reducing frequent price variations and is in the spirit of the random early detection (RED) mechanism used in TCP/IP networks. We observe in our numerical results a considerable improvement in performance using our scheme over that of a recently proposed related scheme in terms of both throughput and delay performance. In particular, our approach exhibits a throughput improvement in the range of 34 to 69 percent in all cases studied (over all routes) over the above scheme.

Power Optimal Network-on-Chip Interconnect Design

A large part of today's multi-core chips is interconnect. Increasing communication complexity has made essential new strategies for interconnects, such as Network on Chip. Power dissipation in interconnects has become a substantial part of the total power dissipation. Techniques to reduce interconnect power have thus become a necessity. In this paper, we present a design methodology that gives values of bus width for interconnect links, frequency of operation for routers, in Network on Chip scenario that satisfy required throughput and dissipate minimal switching power. We develop closed form analytical expressions for the power dissipation, with bus width and frequency as variables and then use Lagrange multiplier method to arrive at the optimal values. We present a 4 port router in 90 nm technology library as case study. The results obtained from analysis are discussed.

Synthesis of plane linkages to generate functions of two variables using point-position reduction—Part 1. Rotary inputs and output

The paper presents simple graphical procedures for position synthesis of plane linkage mechanisms to generate functions of two independent variables. The procedures are based on point-position reduction and permit synthesis of the linkage to satisfy up to six arbitrarily selected precision positions.

Synthesis of plane linkages to generate functions of two variables using point position reduction—II. Sliding inputs and outputs

The paper presents simple graphical procedures for the position synthesis of plane linkage mechanisms with sliding inputs and output to generate functions of two independent variables. The procedures are based on point position reduction and permit synthesis of the linkage to satisfy up to five arbitrarily selected precision positions.

An Integrated Design Procedure for High Frequency AC Inductors for Inverters

Inductors are important energy storage elements that are used as filters in switching power converters. The operating efficiency of power inductors depend on the initial design choices and they remain as one of the most inefficient elements in a power converter. The focus of this paper is to explore the inductor design procedure from the point of efficiency and operating temperature. A modified form of the area product approach is used as starting point for the inductor design. The equations which estimate the power loss in core and copper winding are described. The surface temperature of the inductor is modelled using heat transfer equations for radiation and natural convection. All design assumptions are verified by actual experimental data and results show a good match with the analysis.

M.tuberculosis Pantothenate Kinase: Dual Substrate Specificity and Unusual Changes in Ligand Locations

Kinetic measurements of enzyme activity indicate that type I pantothenate kinase from Mycobacterium tuberculosis has dual substrate specificity for ATP and GTP, unlike the enzyme from Escherichia coli, which shows a higher specificity for ATP. A molecular explanation for the difference in the specificities of the two homologous enzymes is provided by the crystal structures of the complexes of the M. tuberculosis enzyme with (1) GMPPCP and pantothenate, (2) GDP and phosphopantothenate, (3) GDP, (4) GDP and pantothenate, (5) AMPPCP, and (6) GMPPCP, reported here, and the structures of the complexes of the two enzymes involving coenzyme A and different adenyl nucleotides reported earlier. The explanation is substantially based on two critical substitutions in the amino acid sequence and the local conformational change resulting from them. The structures also provide a rationale for the movement of ligands during the action of the mycobacterial enzyme. Dual specificity of the type exhibited by this enzyme is rare. The change in locations of ligands during action,observed in the case of the M. tuberculosis enzyme, is unusual, so is the striking difference between two homologous enzymes in the geometryof the binding site, locations of ligands, and specificity. Furthermore, the dual specificity of the mycobacterial enzyme appears to have been caused by a biological necessity. (C) 2010 Elsevier Ltd.All rights reserved.

Glioblastoma-Specific Protein Interaction Network Identifies PP1A and CSK21 as Connecting Molecules between Cell Cycle-Associated Genes

Glioblastoma (GBM; grade IV astrocytoma) is a very aggressive form of brain cancer with a poor survival and few qualified predictive markers. This study integrates experimentally validated genes that showed specific upregulation in GBM along with their protein-protein interaction information. A system level analysis was used to construct GBM-specific network. Computation of topological parameters of networks showed scale-free pattern and hierarchical organization. From the large network involving 1,447 proteins, we synthesized subnetworks and annotated them with highly enriched biological processes. A careful dissection of the functional modules, important nodes, and their connections identified two novel intermediary molecules CSK21 and protein phosphatase 1 alpha (PP1A) connecting the two subnetworks CDC2-PTEN-TOP2A-CAV1-P53 and CDC2-CAV1-RB-P53-PTEN, respectively. Real-time quantitative reverse transcription-PCR analysis revealed CSK21 to be moderately upregulated and PP1A to be overexpressed by 20-fold in GBM tumor samples. Immunohistochemical staining revealed nuclear expression of PP1A only in GBM samples. Thus, CSK21 and PP1A, whose functions are intimately associated with cell cycle regulation, might play key role in gliomagenesis. Cancer Res; 70(16); 6437-47. (C)2010 AACR.

Interior Medial Axis Transform computation of 3D objects bound by free-form surfaces

This paper presents an algorithm for generating the Interior Medial Axis Transform (iMAT) of 3D objects with free-form boundaries. The algorithm proposed uses the exact representation of the part and generates an approximate rational spline description of the iMAT. The algorithm generates the iMAT by a tracing technique that marches along the object's boundary. The level of approximation is controlled by the choice of the step size in the tracing procedure. Criteria based on distance and local curvature of boundary entities are used to identify the junction points and the search for these junction points is done in an efficient way. The algorithm works for multiply-connected objects as well. Results of the implementation are provided. (C) 2010 Elsevier Ltd. All rights reserved.