Thermal test method for high power three-phase grid-connected inverters

Semiconductor device junction temperatures are maintained within datasheet specified limits to avoid failure in power converters. Burn-in tests are used to ensure this. In inverters, thermal time constants can be large and burn-in tests are required to be performed over long durations of time. At higher power levels, besides increased production cost, the testing requires sources and loads that can handle high power. In this study, a novel method to test a high power three-phase grid-connected inverter is proposed. The method eliminates the need for high power sources and loads. Only energy corresponding to the losses is consumed. The test is done by circulating rated current within the three legs of the inverter. All the phase legs being loaded, the method can be used to test the inverter in both cases of a common or independent cooling arrangement for the inverter phase legs. Further, the method can be used with different inverter configurations - three- or four-wire and for different pulse width modulation (PWM) techniques. The method has been experimentally validated on a 24 kVA inverter for a four-wire configuration that uses sine-triangle PWM and a three-wire configuration that uses conventional space vector PWM.

Injection barrier induced deviations in space charge limited conduction in doped poly(3-methylthiophene) based devices

The carrier density dependent current-voltage (J V) characteristics of electrochemically prepared poly(3-methylthiophene) (P3MeT) have been investigated in Pt/P3MeT/Al devices, as a function of temperature from 280 to 84 K. In these devices, the charge transport is found to be mainly governed by different transport regimes of space charge limited conduction (SCLC). In a lightly doped device, SCLC controlled by exponentially distributed traps (Vl+1 law, l > 1) is observed in the intermediate voltage range (0.5-2 V) at all temperatures. However, at higher bias (> 2 V), the current deviates from the usual Vl+1 law where the slope is found to be less than 2 of the logJ-logV plot, which is attributed to the presence of the injection barrier. These deviations gradually disappear at higher doping level due to reduction in the injection barrier. Numerical simulations of the Vl+1 law by introducing the injection barrier show good agreement with experimental data. The results show that carrier density can tune the charge transport mechanism in Pt/P3MeT/Al devices to understand the non-Ohmic behavior. The plausible reasons for the origin of injection barrier and the transitions in the transport mechanism with carrier density are discussed. (C) 2015 AIP Publishing LLC.

Analysis of sine-triangle and zero-sequence injection modulation schemes for split-phase induction motor drive

A split-phase induction motor is fed from two three-phase voltage source inverters for speed control. This study analyses carrier-comparison based pulse width modulation (PWM) schemes for a split-phase motor drive, from a space-vector perspective. Sine-triangle PWM, one zero-sequence injection PWM where the same zero-sequence signal is used for both the inverters, and another zero-sequence injection PWM where different zero-sequence signals are employed for the two inverters are considered. The set of voltage vectors applied, the sequence in which the voltage vectors are applied, and the resulting current ripple vector are analysed for all the PWM methods. Besides all the PWM methods are compared in terms of dc bus utilisation. For the same three-phase sine reference, the PWM method with different zero-sequence signals for the two inverters is found to employ a set of vectors different from the other methods. Both analysis and experimental results show that this method results in lower total harmonic distortion and higher dc bus utilisation than the other two PWM methods.