A Scalable High Throughput Firewall in FPGA

High end network security applications demand high speed operation and large rule set support. Packet classification is the core functionality that demands high throughput in such applications. This paper proposes a packet classification architecture to meet such high throughput. We have implemented a Firewall with this architecture in reconflgurable hardware. We propose an extension to Distributed Crossproducting of Field Labels (DCFL) technique to achieve scalable and high performance architecture. The implemented Firewall takes advantage of inherent structure and redundancy of rule set by using our DCFL Extended (DCFLE) algorithm. The use of DCFLE algorithm results in both speed and area improvement when it is implemented in hardware. Although we restrict ourselves to standard 5-tuple matching, the architecture supports additional fields. High throughput classification invariably uses Ternary Content Addressable Memory (TCAM) for prefix matching, though TCAM fares poorly in terms of area and power efficiency. Use of TCAM for port range matching is expensive, as the range to prefix conversion results in large number of prefixes leading to storage inefficiency. Extended TCAM (ETCAM) is fast and the most storage efficient solution for range matching. We present for the first time a reconfigurable hardware implementation of ETCAM. We have implemented our Firewall as an embedded system on Virtex-II Pro FPGA based platform, running Linux with the packet classification in hardware. The Firewall was tested in real time with 1 Gbps Ethernet link and 128 sample rules. The packet classification hardware uses a quarter of logic resources and slightly over one third of memory resources of XC2VP30 FPGA. It achieves a maximum classification throughput of 50 million packet/s corresponding to 16 Gbps link rate for the worst case packet size. The Firewall rule update involves only memory re-initialization in software without any hardware change.

Programming an FPGA to Emulate the Dynamics of DC Machines

This paper presents the programming an FPGA (Field Programmable Gate Array) to emulate the dynamics of DC machines. FPGA allows high speed real time simulation with high precision. The described design includes block diagram representation of DC machine, which contain all arithmetic and logical operations. The real time simulation of the machine in FPGA is controlled by user interfaces they are Keypad interface, LCD display on-line and digital to analog converter. This approach provides emulation of electrical machine by changing the parameters. Separately Exited DC machine implemented and experimental results are presented.

FPGA based digital platform for the control of AC drives

This paper presents the new trend of FPGA (Field programmable Gate Array) based digital platform for the control of power electronic systems. There is a rising interest in using digital controllers in power electronic applications as they provide many advantages over their analog counterparts. A board comprising of Cyclone device EP1C12Q240C8 of Altera is used for developing this platform. The details of this board are presented. This developed platform can be used for the controller applications such as UPS, Induction Motor drives and front end converters. A real time simulation of a system can also be done. An open-loop induction motor drive has been implemented using this board and experimental results are presented.

Real-time simulation of electrical machines on FPGA platform

This paper presents real-time simulation models of electrical machines on FPGA platform. Implementation of the real-time numerical integration methods with digital logic elements is discussed. Several numerical integrations are presented. A real-time simulation of DC machine is carried out on this FPGA platform and important transient results are presented. These results are compared to simulation results obtained through a commercial off-line simulation software.

A Scalable High Throughput Firewall in FPGA

High end network security applications demand high speed operation and large rule set support. Packet classification is the core functionality that demands high throughput in such applications. This paper proposes a packet classification architecture to meet such high throughput. We have Implemented a Firewall with this architecture in reconfigurable hardware. We propose an extension to Distributed Crossproducting of Field Labels (DCFL) technique to achieve scalable and high performance architecture. The implemented Firewall takes advantage of inherent structure and redundancy of rule set by using, our DCFL Extended (DCFLE) algorithm. The use of DCFLE algorithm results In both speed and area Improvement when It is Implemented in hardware. Although we restrict ourselves to standard 5-tuple matching, the architecture supports additional fields.High throughput classification Invariably uses Ternary Content Addressable Memory (TCAM) for prefix matching, though TCAM fares poorly In terms of area and power efficiency. Use of TCAM for port range matching is expensive, as the range to prefix conversion results in large number of prefixes leading to storage inefficiency. Extended TCAM (ETCAM) is fast and the most storage efficient solution for range matching. We present for the first time a reconfigurable hardware Implementation of ETCAM. We have implemented our Firewall as an embedded system on Virtex-II Pro FPGA based platform, running Linux with the packet classification in hardware. The Firewall was tested in real time with 1 Gbps Ethernet link and 128 sample rules. The packet classification hardware uses a quarter of logic resources and slightly over one third of memory resources of XC2VP30 FPGA. It achieves a maximum classification throughput of 50 million packet/s corresponding to 16 Gbps link rate for file worst case packet size. The Firewall rule update Involves only memory re-initialiization in software without any hardware change.

Dark Spots, Bubbles, and Shells in the Lobes of Extragalactic Radio Sources

Based on maps of the extragalactic radio sources Cyg A, Her A, Cen A, 3C 277.3 and others, arguments are given that the twin-jets from the respective active galactic nucleus ram their channels repeatedly through thin, massive shells. The jets are thereby temporarily choked and blow radio bubbles. Warm shell matter in the cocoon shows up radio-dark through electron-scattering.

Mössbauer Lineshape in the Presence of Radio-Frequency Fields

A general expression for the Mössbauer lineshape in the presence of a radio frequency field is derived. As an example the effect of the rf field on Fe57 nuclei is discussed for a situation where the 3/2 sublevel of 14.4 keV state of Fe57 is selectively populated. At resonance, both the diagonal and non-diagonal matrix elements contribute to the correlation function. As a result, in addition to a slight rf induced distortion of the main Mössbauer line. additional transition lines are obtained. Thus the present calculation supports the experimental observations of Heiman et al.

Radio frequency emission in electron beam-plasma and beam-beam interaction

A linear excitation of electromagnetic modes at frequencies (n + ı89 in a plasma through which two electron beams are contra-streaming along the magnetic field is investigated. This may be a source of the observed {cote emissions at auroral latitudes.

The interference environment of radio Noise froh4 lightning

The paper furnishes a review and air ovendepr "f radio noise *om lightning as rr so~irce of interference to analogue and digital Corn?tunicatioiz. The parameters of fhe different fornls < f, noise necessary .for pssessigth e interfering effect of the rloise are described. 4railublr irfjrncroiun thrr tndevstor71zs, thunder-clouds, convecrion cells and lightning are er ieveadn d their liizitatimsp ointed oui. Thew fol101r.s a descripiicn of how the source, popugafiona nd receiver chaacteristidse termine the sfrticture qf a/rnosplro.ic noise as receiwd at a point of observation. The tratrrral unit for this noise i.s the mise burst rtrising from o w complete lightning.flas4. The pmuneters of the nrise birrst as a 11.hole and its structure ctetennine the inrqfflrrence enrirnniient. A hisforic reriel$. qf t2sophericii oke .studies sho1(5 that it i. wrreirt(v of importance oldy in thc ropicarl egions of' the wr ldf i>rs hichf hc neailable data are wry defective. New data are ficnrished. The contribution of atmospheric noise for backgrouzd interference even in remote places ,for r.adicj astronomy at VHF is firrnished. The imporlance of aimcspizeric nctise cceurring ;vporadiea@ in high values fur slzort inier.als at VHF and higher frequencies in the tropics is brought out.

Redefine: Runtime Reconfigurable Polymorphic ASIC

Emerging embedded applications are based on evolving standards (e.g., MPEG2/4, H.264/265, IEEE802.11a/b/g/n). Since most of these applications run on handheld devices, there is an increasing need for a single chip solution that can dynamically interoperate between different standards and their derivatives. In order to achieve high resource utilization and low power dissipation, we propose REDEFINE, a polymorphic ASIC in which specialized hardware units are replaced with basic hardware units that can create the same functionality by runtime re-composition. It is a ``future-proof'' custom hardware solution for multiple applications and their derivatives in a domain. In this article, we describe a compiler framework and supporting hardware comprising compute, storage, and communication resources. Applications described in high-level language (e.g., C) are compiled into application substructures. For each application substructure, a set of compute elements on the hardware are interconnected during runtime to form a pattern that closely matches the communication pattern of that particular application. The advantage is that the bounded CEs are neither processor cores nor logic elements as in FPGAs. Hence, REDEFINE offers the power and performance advantage of an ASIC and the hardware reconfigurability and programmability of that of an FPGA/instruction set processor. In addition, the hardware supports custom instruction pipelining. Existing instruction-set extensible processors determine a sequence of instructions that repeatedly occur within the application to create custom instructions at design time to speed up the execution of this sequence. We extend this scheme further, where a kernel is compiled into custom instructions that bear strong producer-consumer relationship (and not limited to frequently occurring sequences of instructions). Custom instructions, realized as hardware compositions effected at runtime, allow several instances of the same to be active in parallel. A key distinguishing factor in majority of the emerging embedded applications is stream processing. To reduce the overheads of data transfer between custom instructions, direct communication paths are employed among custom instructions. In this article, we present the overview of the hardware-aware compiler framework, which determines the NoC-aware schedule of transports of the data exchanged between the custom instructions on the interconnect. The results for the FFT kernel indicate a 25% reduction in the number of loads/stores, and throughput improves by log(n) for n-point FFT when compared to sequential implementation. Overall, REDEFINE offers flexibility and a runtime reconfigurability at the expense of 1.16x in power and 8x in area when compared to an ASIC. REDEFINE implementation consumes 0.1x the power of an FPGA implementation. In addition, the configuration overhead of the FPGA implementation is 1,000x more than that of REDEFINE.

Three-User Cognitive Channels with Cumulative Message Sharing: An Achievable Rate Region

In this paper, an achievable rate region for the three-user discrete memoryless interference channel with asymmetric transmitter cooperation is derived. The three-user channel facilitates different ways of message sharing between the transmitters. We introduce a manner of noncausal (genie aided) unidirectional message-sharing, which we term cumulative message sharing. We consider receivers with predetermined decoding capabilities, and define a cognitive interference channel. We then derive an achievable rate region for this channel by employing a coding scheme which is a combination of superposition and Gel'fand-Pinsker coding techniques.

Some pulse characteristics of atmospheric radio noise bursts at 3 MHz

An atmospheric radio noise burst represents the radiation received from one complete lightning flash at the frequency to which a receiver is tuned and within the receiver bandwidth. At tropical latitudes, the principal source of interference in the frequency range from 0.1 to 10 MHz is the burst form of atmospheric radio noise. The structure of a burst shows several approximately rectangular pulses of random amplitude, duration and frequency of recurrence. The influence of the noise on data communication can only be examined when the value of the number of pulses crossing a certain amplitude threshold per unit time of the noise burst is known. A pulse rate counter designed for this purpose has been used at Bangalore (12°58′N, 77°35′E) to investigate the pulse characteristics of noise bursts at 3 MHz with a receiver bandwidth of 3.3 kHz/6d B. The results show that the number of pulses lying in the amplitude range between peak and quasi-peak values of the noise bursts and the burst duration corresponding to these pulses follow log normal distributions. The pulse rates deduced therefrom show certain correlation between the number of pulses and the duration of the noise burst. The results are discussed with a view to furnish necessary information for data communication.

Real-Time Simulation of Electrical Machines on FPGA Platform

This paper presents real-time simulation models of electrical machines on FPGA platform. Implementation of the real-time numerical integration methods with digital logic elements is discussed. Several numerical integrations are presented. A real-time simulation of DC machine is carried out on this FPGA platform and important transient results are presented. These results are compared to simulation results obtained through a commercial off-line simulation software

Starburst in the ultraluminous galaxy Arp 220: Constraints from observations of radio recombination lines and continuum

We present observations of radio recombination lines (RRL) from the starburst galaxy Arp 220 at 8.1 GHz (H92 alpha) and 1.4 GHz (H167 alpha and H165 alpha) and at 84 GHz (H42 alpha), 96 GHz (H40 alpha) and 207 GHz (H31 alpha) using the Very Large Array and the IRAM 30 m telescope, respectively. RRLs were detected at all the frequencies except 1.4 GHz, where a sensitive upper limit was obtained. We also present continuum flux measurements at these frequencies as well as at 327 MHz made with the VLA. The continuum spectrum, which has a spectral index alpha similar to -0.6 (S-nu proportional to nu(alpha)) between 5 and 10 GHz, shows a break near 1.5 GHz, a prominent turnover below 500 MHz, and a flatter spectral index above 50 GHz. We show that a model with three components of ionized gas with different densities and area covering factors can consistently explain both RRL and continuum data. The total mass of ionized gas in the three components is 3.2 x 10(7) M., requiring 3 x 10(5) O5 stars with a total Lyman continuum production rate N-Lyc similar to 1.3 x 10(55) photons s(-1). The ratio of the expected to observed Br alpha and Br gamma fluxes implies a dust extinction A(V) similar to 45 mag. The derived Lyman continuum photon production rate implies a continuous star formation rate (SFR) averaged over the lifetime of OB stars of similar to 240 M yr(-1). The Lyman continuum photon Production rate of similar to 3% associated with the high-density H II regions implies a similar SFR at recent epochs (t < 10(5) yr). An alternative model of high-density gas, which cannot be excluded on the basis of the available data, predicts 10 times higher SFR at recent epochs. If confirmed, this model implies that star formation in Arp 220 consists of multiple starbursts of very high SFR (few times 10(3) M. yr(-1)) and short duration (similar to 10(5) yr). The similarity of IR excess, L-IR/L-Ly alpha similar to 24, in Arp 220 to values observed in starburst galaxies shows that most of the high luminosity of Arp 220 is due to the ongoing starburst rather than to a hidden active galactic nucleus (AGN). A comparison of the IR excesses in Arp 220, the Galaxy, and M33 indicates that the starburst in Arp 220 has an initial mass function that is similar to that in normal galaxies and has a duration longer than 107 yr. If there was no infall of gas during this period, then the star formation efficiency (SFE) in Arp 220 is similar to 50%. The high SFR and SFE in Arp 220 is consistent with their known dependences on mass and density of gas in star-forming regions of normal galaxies.

A multi-station satellite radio beacon study of ionospheric variations during total solar eclipses

Faraday rotation data obtained at Delhi, Kurukshetra, Hyderabad, Bangalore, Waltair, Nagpur and Calcutta during the total solar eclipse of 16 February 1980 and at Delhi during the total solar eclipse of 31 July 1981 have been analysed to detect the gravity waves generated by a total solar eclipse as hypothesized by Chimonas and Hines (1970, J. geophys. Res. 75, 875). It has been found that gravity waves can be generated by a total solar eclipse but their detection at ionospheric heights is critically dependent on the location of the observing station in relation to the eclipse path geometry. The distance of the observing station from the eclipse path should be more than 500 km in order to detect such gravity waves.