Roles for Transcription Factors Sp1, NF-kappa B, IRF3, and IRF7 in Expression of the Human IFNL4 Gene

The expression of a biologically active human IFN4 depends on the presence of a frameshift deletion polymorphism within the first exon of the interferon lambda 4 (IFNL4) gene. In this report, we use the lung carcinoma-derived cell line, A549, which is genetically viable to express a functional IFN4, to address transcriptional requirements of the IFNL4 gene. We show that the GC-rich DNA-binding transcription factor (TF) specificity protein 1 (Sp1) is recruited to the IFNL4 promoter and has a role in induction of gene expression upon stimulation with viral RNA mimic poly(I:C). By using RNAi and overexpression strategies, we also show key roles in IFNL4 gene expression for the virus-inducible TFs, nuclear factor kappa-light-chain-enhancer of activated B cells (NF-B), IFN regulatory factor 3 (IRF3), and IRF7. Interestingly, we also observe that overexpression of IFN4 influences IFNL4 promoter activity, which may further be dependent on the retinoic acid-inducible gene-I (RIG-I)-like receptor pathway. Together, our work for the first time reports on the functional characterization of the human IFNL4 promoter.

Accelerating method of moments based package-board 3D parasitic extraction using FPGA

In this article, a Field Programmable Gate Array (FPGA)-based hardware accelerator for 3D electromagnetic extraction, using Method of Moments (MoM) is presented. As the number of nets or ports in a system increases, leading to a corresponding increase in the number of right-hand-side (RHS) vectors, the computational cost for multiple matrix-vector products presents a time bottleneck in a linear-complexity fast solver framework. In this work, an FPGA-based hardware implementation is proposed toward a two-level parallelization scheme: (i) matrix level parallelization for single RHS and (ii) pipelining for multiple-RHS. The method is applied to accelerate electrostatic parasitic capacitance extraction of multiple nets in a Ball Grid Array (BGA) package. The acceleration is shown to be linearly scalable with FPGA resources and speed-ups over 10x against equivalent software implementation on a 2.4GHz Intel Core i5 processor is achieved using a Virtex-6 XC6VLX240T FPGA on Xilinx's ML605 board with the implemented design operating at 200MHz clock frequency. (c) 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:776-783, 2016