Stable p-type conductivity in B and N co-doped ZnO epitaxial thin film

We report on the observation of stable p-type conductivity in B and N co-doped epitaxial ZnO thin films grown by pulsed laser deposition. Films grown at higher oxygen partial pressure (similar to 10(-1) Torr) shows p-type conductivity with a carrier concentration of similar to 3 x 10(16) cm(-3). This p-type conductivity is associated with the significant decrease in defect emission peaks due to the vacancy oxygen (V-O) and Schottky type-I native defects compared to films grown at low oxygen partial pressure (similar to 10(-5) Torr). The p-type conductivity is explained with the help of density functional theory (DFT) calculation considering off-stoichiometric BN1+x in the ZnO lattice. (C) 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Design Optimization of Thin-Film Transistors Based on a Metal-Substrate-Semiconductor Architecture for High DC Voltage Sensing

We discuss the potential application of high dc voltage sensing using thin-film transistors (TFTs) on flexible substrates. High voltage sensing has potential applications for power transmission instrumentation. For this, we consider a gate metal-substrate-semiconductor architecture for TFTs. In this architecture, the flexible substrate not only provides mechanical support but also plays the role of the gate dielectric of the TFT. Hence, the thickness of the substrate needs to be optimized for maximizing transconductance, minimizing mechanical stress, and minimizing gate leakage currents. We discuss this optimization, and develop n-type and p-type organic TFTs using polyvinyldene fluoride as the substrate-gate insulator. Circuits are also realized to achieve level shifting, amplification, and high drain voltage operation.

Curvature Management in Buffer Layer for Device Quality GaN Growth on Si (111)

An efficient buffer layer scheme has been designed to address the issue of curvature management during metalorganic chemical vapour deposition growth of GaN on Si (111) substrate. This is necessary to prevent cracking of the grown layer during post-growth cooling down from growth temperature to room temperature and to achieve an allowable bow (<40 m) in the wafer for carrying out lithographic processes. To meet both these ends simultaneously, the stress evolution in the buffer layers was observed carefully. The reduction in precursor flow during the buffer layer growth provided better control over curvature evolution in the growing buffer layers. This has enabled the growth of a suitable high electron mobility transistor (HEMT) stack on 2'' Si (111) substrate of 300 m thickness with a bow as low as 11.4 m, having a two-dimensional electron gas (2DEG) of mobility, carrier concentration, and sheet resistance values 1510 cm(2)/V-s, 0.96 x 10(13)/cm(2), and 444 /, respectively. Another variation of similar technique resulted in a bow of 23.4 m with 2DEG mobility, carrier concentration, and sheet resistance values 1960 cm(2)/V-s, 0.98 x 10(13)/cm(2), and 325 /, respectively.

Low temperature solution processed high-kappa ZrO2 gate dielectrics for nanoelectonics

The high-kappa gate dielectrics, specifically amorphous films offer salient features such as exceptional mechanical flexibility, smooth surfaces and better uniformity associated with low leakage current density. In this work, similar to 35 nm thick amorphous ZrO2 films were deposited on silicon substrate at low temperature (300 degrees C, 1 h) from facile spin-coating method and characterized by various analytical techniques. The X-ray diffraction and X-ray photoelectron spectroscopy reveal the formation of amorphous phase ZrO2, while ellipsometry analysis together with the Atomic Force Microscope suggest the formation of dense film with surface roughness of 1.5 angstrom, respectively. The fabricated films were integrated in metal-oxide-semiconductor (MOS) structures to check the electrical capabilities. The oxide capacitance (C-ox), flat band capacitance (C-FB), flat band voltage (V-FB), dielectric constant (kappa) and oxide trapped charges (Q(ot)) extracted from high frequency (1 MHz) C-V curve are 186 pF, 104 pF, 0.37V, 15 and 2 x 10(-11) C, respectively. The small flat band voltage 0.37V, narrow hysteresis and very little frequency dispersion between 10 kHz-1 MHz suggest an excellent a-ZrO2/Si interface with very less trapped charges in the oxide. The films exhibit a low leakage current density 4.7 x 10(-9)A/cm(2) at 1V. In addition, the charge transport mechanism across the MOSC is analyzed and found to have a strong bias dependence. The space charge limited conduction mechanism is dominant in the high electric field region (1.3-5 V) due to the presence of traps, while the trap-supported tunneling is prevailed in the intermediate region (0.35-1.3 V). Low temperature solution processed ZrO2 thin films obtained are of high quality and find their importance as a potential dielectric layer on Si and polymer based flexible electronics. (C) 2016 Published by Elsevier B.V.