Load Balancing with Availability Checker and Load Reporters (LB-ACLRs) for improved Performance in Distributed Systems

Distributed system has quite a lot of servers to attain increased availability of service and for fault tolerance. Balancing the load among these servers is an important task to achieve better performance. There are various hardware and software based load balancing solutions available. However there is always an overhead on Servers and the Load Balancer while communicating with each other and sharing their availability and the current load status information. Load balancer is always busy in listening to clients' request and redirecting them. It also needs to collect the servers' availability status frequently, to keep itself up-to-date. Servers are busy in not only providing service to clients but also sharing their current load information with load balancing algorithms. In this paper we have proposed and discussed the concept and system model for software based load balancer along with Availability-Checker and Load Reporters (LB-ACLRs) which reduces the overhead on server and the load balancer. We have also described the architectural components with their roles and responsibilities. We have presented a detailed analysis to show how our proposed Availability Checker significantly increases the performance of the system.

A Bacterial Foraging Optimization and Learning Automata Based Feature Selection for Motor Imagery EEG Classification

Selection of relevant features is an open problem in Brain-computer interfacing (BCI) research. Sometimes, features extracted from brain signals are high dimensional which in turn affects the accuracy of the classifier. Selection of the most relevant features improves the performance of the classifier and reduces the computational cost of the system. In this study, we have used a combination of Bacterial Foraging Optimization and Learning Automata to determine the best subset of features from a given motor imagery electroencephalography (EEG) based BCI dataset. Here, we have employed Discrete Wavelet Transform to obtain a high dimensional feature set and classified it by Distance Likelihood Ratio Test. Our proposed feature selector produced an accuracy of 80.291% in 216 seconds.

Ultrasonic Guided Wave Sensor Network Optimization for Monitoring Rivet Line

Guided waves using piezo-electric wafer active sensors (PWAS) is one of the useful techniques of damage detection. Sensor network optimization with minimal network hardware footprint and maximal area of coverage remains a challenging problem. PWAS sensors are placed at discrete locations in order to inspect damages in plates and the idea has the potential to be extended to assembled structures. Various actuator-sensor configurations are possible within the network in order to identify and locate damages. In this paper we present a correlation based approach to monitor cracks emanating from rivet line using a simulated guided wave signal whose sensor is operating in pulse echo mode. Discussions regarding the identification of phase change due to reflections from the crack are also discussed in this paper.

Optimization of bus allocation to depots by minimizing dead kilometers

In metropolitan cities, public transportation service plays a vital role in mobility of people, and it has to introduce new routes more frequently due to the fast development of the city in terms of population growth and city size. Whenever there is introduction of new route or increase in frequency of buses, the nonrevenue kilometers covered by the buses increases as depot and route starting/ending points are at different places. This non-revenue kilometers or dead kilometers depends on the distance between depot and route starting point/ending point. The dead kilometers not only results in revenue loss but also results in an increase in the operating cost because of the extra kilometers covered by buses. Reduction of dead kilometers is necessary for the economic growth of the public transportation system. Therefore, in this study, the attention is focused on minimizing dead kilometers by optimizing allocation of buses to depots depending upon the shortest distance between depot and route starting/ending points. We consider also depot capacity and time period of operation during allocation of buses to ensure parking safety and proper maintenance of buses. Mathematical model is developed considering the aforementioned parameters, which is a mixed integer program, and applied to Bangalore Metropolitan Transport Corporation (BMTC) routes operating presently in order to obtain optimal bus allocation to depots. Database for dead kilometers of depots in BMTC for all the schedules are generated using the Form-4 (trip sheet) of each schedule to analyze depot-wise and division-wise dead kilometers. This study also suggests alternative locations where depots can be located to reduce dead kilometers. Copyright (C) 2015 John Wiley & Sons, Ltd.

Uplift Resistance of Interfering Pipelines Buried in Sand

The vertical uplift resistance of interfering pipelines buried in sands has been computed using the lower-bound limit analysis in conjunction with finite elements and nonlinear optimization. The soil mass is assumed to follow the Mohr-Coulomb failure criterion and an associated flow rule. It is specified that all the pipes fail simultaneously at the same magnitude of the failure load. For different clear spacing (S) between the pipes, the magnitude of the efficiency factor (xi(gamma)) is determined. Because of pipes' interference, with a reduction in the spacing between the pipelines, the magnitude of xi(gamma) is found to decrease continuously. The results were found to compare quite well with the available data from literature for horizontal strip anchors. (C) 2015 American Society of Civil Engineers.

A Simple Hysteretic Energy Harvesting Method for Nonneutral AC Switches in Load Automation

This paper presents a simple hysteretic method to obtain the energy required to operate the gate-drive, sensors, and other circuits within nonneutral ac switches intended for use in load automated buildings. The proposed method features a switch-mode low part-count self-powered MOSFET ac switch that achieves efficiency and load current THD figures comparable to those of an externally gate-driven switch built using similar MOSFETS. The fundamental operation of the method is explained in detail, followed by the modifications required for practical implementation. Certain design rules that allow the method to accommodate a wide range of single-phase loads from 10 VA to 1 kVA are discussed, along with an efficiency enhancement feature based on inherent MOSFET characteristics. The limitations and side effects of the method are also mentioned according to their levels of severity. Finally, experimental results obtained using a prototype sensor switch are presented, along with a performance comparison of the prototype with an externally gate-driven MOSFET switch.

PolyMage: Automatic Optimization for Image Processing Pipelines

This paper presents the design and implementation of PolyMage, a domain-specific language and compiler for image processing pipelines. An image processing pipeline can be viewed as a graph of interconnected stages which process images successively. Each stage typically performs one of point-wise, stencil, reduction or data-dependent operations on image pixels. Individual stages in a pipeline typically exhibit abundant data parallelism that can be exploited with relative ease. However, the stages also require high memory bandwidth preventing effective utilization of parallelism available on modern architectures. For applications that demand high performance, the traditional options are to use optimized libraries like OpenCV or to optimize manually. While using libraries precludes optimization across library routines, manual optimization accounting for both parallelism and locality is very tedious. The focus of our system, PolyMage, is on automatically generating high-performance implementations of image processing pipelines expressed in a high-level declarative language. Our optimization approach primarily relies on the transformation and code generation capabilities of the polyhedral compiler framework. To the best of our knowledge, this is the first model-driven compiler for image processing pipelines that performs complex fusion, tiling, and storage optimization automatically. Experimental results on a modern multicore system show that the performance achieved by our automatic approach is up to 1.81x better than that achieved through manual tuning in Halide, a state-of-the-art language and compiler for image processing pipelines. For a camera raw image processing pipeline, our performance is comparable to that of a hand-tuned implementation.

Conversion of plastic waste into CNTs using Ni/Mo/MgO catalystAn optimization approach by mixture experiment

A combustion technique is used to study the synthesis of carbon nano tubes from waste plastic as a precursor and Ni/Mo/MgO as a catalyst. The catalytic activity of three components Ni, Mo, MgO is measured in terms of amount of carbon product obtained. Different proportions of metal ions are optimized using mixture experiment in Design expert software. D-optimal design technique is adopted due to nonsimplex region and presence of constraints in the mixture experiment. The activity of the components is observed to be interdependent and the component Ni is found to be more effective. The catalyst containing Ni0.8Mo0.1MgO0.1 yields more carbon product. The structure of catalyst and CNTs are studied by using SEM, XRD, and Raman spectroscopy. SEM analysis shows the formation of longer CNTs with average diameter of 40-50 nm.

Design Optimization of Thin-Film Transistors Based on a Metal-Substrate-Semiconductor Architecture for High DC Voltage Sensing

We discuss the potential application of high dc voltage sensing using thin-film transistors (TFTs) on flexible substrates. High voltage sensing has potential applications for power transmission instrumentation. For this, we consider a gate metal-substrate-semiconductor architecture for TFTs. In this architecture, the flexible substrate not only provides mechanical support but also plays the role of the gate dielectric of the TFT. Hence, the thickness of the substrate needs to be optimized for maximizing transconductance, minimizing mechanical stress, and minimizing gate leakage currents. We discuss this optimization, and develop n-type and p-type organic TFTs using polyvinyldene fluoride as the substrate-gate insulator. Circuits are also realized to achieve level shifting, amplification, and high drain voltage operation.

SMO: An Integrated Approach to Intra-array and Inter-array Storage Optimization

The polyhedral model provides an expressive intermediate representation that is convenient for the analysis and subsequent transformation of affine loop nests. Several heuristics exist for achieving complex program transformations in this model. However, there is also considerable scope to utilize this model to tackle the problem of automatic memory footprint optimization. In this paper, we present a new automatic storage optimization technique which can be used to achieve both intra-array as well as inter-array storage reuse with a pre-determined schedule for the computation. Our approach works by finding statement-wise storage partitioning hyper planes that partition a unified global array space so that values with overlapping live ranges are not mapped to the same partition. Our heuristic is driven by a fourfold objective function which not only minimizes the dimensionality and storage requirements of arrays required for each high-level statement, but also maximizes inter statement storage reuse. The storage mappings obtained using our heuristic can be asymptotically better than those obtained by any existing technique. We implement our technique and demonstrate its practical impact by evaluating its effectiveness on several benchmarks chosen from the domains of image processing, stencil computations, and high-performance computing.