Penetration of hydromagnetic energy deep into the magnetosphere

Magnetometer data, acquired on spacecraft and simultaneously at high and low latitudes on the ground, are compared in order to study the propagation characteristics of hydromagnetic energy deep into the magnetosphere. Single events provide evidence that wave energy at L ∼ 3 can at times be only one order of magnitude lower than at L ∼ 13. In addition, statistical analyses of the H-component groundbased data obtained during local daytime hours of 17 July-3 August 1985 show that wave amplitudes at L ∼ 3 are generally 10-30 times lower than at L ∼ 13. The L-dependence of near-equator magnetic field fluctuations measured on ISEE-2 show a sharp drop in energy near the magnetopause and a more gradual fall-off of energy deeper inside the magnetosphere. Such high levels of wave power deep in the magnetosphere have not been quantitatively understood previously. Our initial attempt is to calculate the decay length of an evanescent wave generated at a thick magnetopause boundary. Numerical calculations show that fast magnetosonic modes (called magnetopause and inner mode) can be generated under very restrictive conditions for the field and plasma parameters. These fast compressional modes may have their energy reduced by only one order of magnitude over a penetration depth of about 8RE. More realistic numerical simulations need to be carried out to see whether better agreement with the data can be attained.

Analysis of network architectures for zigbee sensor clusters

We provide a comparative performance analysis of network architectures for beacon enabled Zigbee sensor clusters using the CSMA/CA MAC defined in the IEEE 802.15.4 standard, and organised as (i) a star topology, and (ii) a two-hop topology. We provide analytical models for obtaining performance measures such as mean network delay, and mean node lifetime. We find that the star topology is substantially superior both in delay performance and lifetime performance than the two-hop topology.

System effects in double‐channel gated‐integrator‐based deep‐level transient spectroscopy

The effects of the two sampling gate positions, and their widths and the integrator response times on the position, height, and shape of the peaks obtained in a double‐channel gated‐integrator‐based deep‐level transient spectroscopy (DLTS) system are evaluated. The best compromise between the sensitivity and the resolution of the DLTS system is shown to be obtained when the ratio of the two sampling gate positions is about 20. An integrator response time of about 100 ms is shown to be suitable for practical values of emission time constants and heating rates generally used.

Control of barrier height of MIS tunnel diodes using deep level impurities

The barrier height of MIS tunnel diodes is studied considering the effect of deep impurities. It is shown that the barrier height of a given MIS-system can be controlled by changing the density and the activation energy of the defect level. The study leads to the conclusion that deep impurities of character opposite to shallow impurities enhance the barrier height. On the other hand, the barrier height is lowered when the type of the deep impurities is the same as that of shallow impurities.

Silver- and Gold-Related Deep Levels in Gallium Arsenide

Characterization of silver- and gold-related defects in gallium arsenide is carried out. These impurities were introduced during the thermal diffusion process and the related defects are characterized by deep-level transient spectroscopy and photoluminescence. The silver-related center in GaAs shows a 0.238 eV photoluminescence line corresponding to no-phonon transition, whereas its thermal ionization energy is found to be 0.426 eV. The thermal activation energy of the gold-related center in GaAs is 0.395 eV, but there is no corresponding luminescence signal.

Single‐gate deep level transient spectroscopy technique

A new deep level transient spectroscopy technique is suggested which allows the deep level parameters to be obtained from a single temperature scan. Using large ratio t2/t1 of the measurement gate positions t1 and t2 and analyzing the steep high‐temperature side of the peak, it is demonstrated that the deep level activation energy can be determined with high accuracy.

Compiler-assisted power optimization for clustered VLIW architectures

Clustered VLIW architectures solve the scalability problem associated with flat VLIW architectures by partitioning the register file and connecting only a subset of the functional units to a register file. However, inter-cluster communication in clustered architectures leads to increased leakage in functional components and a high number of register accesses. In this paper, we propose compiler scheduling algorithms targeting two previously ignored power-hungry components in clustered VLIW architectures, viz., instruction decoder and register file. We consider a split decoder design and propose a new energy-aware instruction scheduling algorithm that provides 14.5% and 17.3% benefit in the decoder power consumption on an average over a purely hardware based scheme in the context of 2-clustered and 4-clustered VLIW machines. In the case of register files, we propose two new scheduling algorithms that exploit limited register snooping capability to reduce extra register file accesses. The proposed algorithms reduce register file power consumption on an average by 6.85% and 11.90% (10.39% and 17.78%), respectively, along with performance improvement of 4.81% and 5.34% (9.39% and 11.16%) over a traditional greedy algorithm for 2-clustered (4-clustered) VLIW machine. (C) 2010 Elsevier B.V. All rights reserved.

Comparative-Study of Photonic Switching architectures

The basic photonic switching elements of practical importance are outlined. A detailed comparative study of photonic switching architectures is presented both for guided wave fabrics and free-space fabrics. The required equations for comparative study are obtained, after considering the parameters like bend losses, effects of waveguide crossings, etc. The potential areas of application of photonic switching are pointed out.

Tropical deep convection, convective available potential energy and sea surface temperature

The convective available potential energy (CAFE) based on monthly mean sounding has been shown to be relevant to deep convection in the tropics. The variation of CAFE with SST has been found to be similar to the variation of the frequency of deep convection at one station each in the tropical Atlantic and W. Pacific oceans. This suggests a strong link between the frequency of tropical convection and CAFE. It has been shown that CAFE so derived can be interpreted as the work potential of the atmosphere above the boundary layer with ascent in the convective region and subsidence in the surrounding cloud-free region.

Scheduling expression trees with reusable registers on delayed-load architectures

In this paper, we look at the problem of scheduling expression trees with reusable registers on delayed load architectures. Reusable registers come into the picture when the compiler has a data-flow analyzer which is able to estimate the extent of use of the registers. Earlier work considered the same problem without allowing for register variables. Subsequently, Venugopal considered non-reusable registers in the tree. We further extend these efforts to consider a much more general form of the tree. We describe an approximate algorithm for the problem. We formally prove that the code schedule produced by this algorithm will, in the worst case, generate one interlock and use just one more register than that used by the optimal schedule. Spilling is minimized. The approximate algorithm is simple and has linear complexity.

Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay

The use of delayed coefficient adaptation in the least mean square (LMS) algorithm has enabled the design of pipelined architectures for real-time transversal adaptive filtering. However, the convergence speed of this delayed LMS (DLMS) algorithm, when compared with that of the standard LMS algorithm, is degraded and worsens with increase in the adaptation delay. Existing pipelined DLMS architectures have large adaptation delay and hence degraded convergence speed. We in this paper, first present a pipelined DLMS architecture with minimal adaptation delay for any given sampling rate. The architecture is synthesized by using a number of function preserving transformations on the signal flow graph representation of the DLMS algorithm. With the use of carry-save arithmetic, the pipelined architecture can support high sampling rates, limited only by the delay of a full adder and a 2-to-1 multiplexer. In the second part of this paper, we extend the synthesis methodology described in the first part, to synthesize pipelined DLMS architectures whose power dissipation meets a specified budget. This low-power architecture exploits the parallelism in the DLMS algorithm to meet the required computational throughput. The architecture exhibits a novel tradeoff between algorithmic performance (convergence speed) and power dissipation. (C) 1999 Elsevier Science B.V. All rights resented.

Mapping adaptive resonance theory onto ring and mesh architectures

In recent years, parallel computers have been attracting attention for simulating artificial neural networks (ANN). This is due to the inherent parallelism in ANN. This work is aimed at studying ways of parallelizing adaptive resonance theory (ART), a popular neural network algorithm. The core computations of ART are separated and different strategies of parallelizing ART are discussed. We present mapping strategies for ART 2-A neural network onto ring and mesh architectures. The required parallel architecture is simulated using a parallel architectural simulator, PROTEUS and parallel programs are written using a superset of C for the algorithms presented. A simulation-based scalability study of the algorithm-architecture match is carried out. The various overheads are identified in order to suggest ways of improving the performance. Our main objective is to find out the performance of the ART2-A network on different parallel architectures. (C) 1999 Elsevier Science B.V. All rights reserved.

Studies on process induced deep levels in silicon

An attempt was made to study the deep level impurities and defects introduced into thyristor grade silicon under different processing conditions. DLTS, C-V and I-V measurements were carried out. The ideality factors of the diodes is around 1-7. Activation energy, trap density and minority carrier lifetime were measured.

Scheduling expression trees for delayed-load architectures

In this paper we consider the problem of scheduling expression trees on delayed-load architectures. The problem tackled here takes root from the one considered in [Proceedings of the ACM SIGPLAN '91 Conf. on Programming Language Design and Implementation, 1991. p. 256] in which the leaves of the expression trees all refer to memory locations. A generalization of this involves the situation in which the trees may contain register variables, with the registers being used only at the leaves. Solutions to this generalization are given in [ACM Trans. Prog. Lang. Syst. 17 (1995) 740, Microproc. Microprog. 40 (1994) 577]. This paper considers the most general case in which the registers are reusable. This problem is tackled in [Comput. Lang, 21 (1995) 49] which gives an approximate solution to the problem under certain assumptions about the contiguity of the evaluation order: Here we propose an optimal solution (which may involve even a non-contiguous evaluation of the tree). The schedule generated by the algorithm given in this paper is optimal in the sense that it is an interlock-free schedule which uses the minimum number of registers required. An extension to the algorithm incorporates spilling. The problem as stated in this paper is an instruction scheduling problem. However, the problem could also be rephrased as an operations research problem with a difference in terminology. (C) 2002 Elsevier Science B.V. All rights reserved.