Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations

We investigate the feasibility of developing a comprehensive gate delay and slew models which incorporates output load, input edge slew, supply voltage, temperature, global process variations and local process variations all in the same model. We find that the standard polynomial models cannot handle such a large heterogeneous set of input variables. We instead use neural networks, which are well known for their ability to approximate any arbitrary continuous function. Our initial experiments with a small subset of standard cell gates of an industrial 65 nm library show promising results with error in mean less than 1%, error in standard deviation less than 3% and maximum error less than 11% as compared to SPICE for models covering 0.9- 1.1 V of supply, -40degC to 125degC of temperature, load, slew and global and local process parameters. Enhancing the conventional libraries to be voltage and temperature scalable with similar accuracy requires on an average 4x more SPICE characterization runs.

Modeling wrap faced reinforced soil retaining walls subjected to dynamic excitation

This paper describes some of the physical and numerical model tests of reinforced soil retaining walls subjected to dynamic excitation through uni-axial shaking tests. Models of retaining walls are constructed in a perspex box with geotextile reinforcement using the wrap around technique with dry sand backfill and instrumented with displacement sensors, accelerometers and soil pressure sensors. Numerical modelling of these shaking table tests is carried using FLAC. Numerical model is validated by comparing physical model results. Responses of wrap faced walls with different number of reinforcement layers are discussed from both the physical and numerical model tests. Results showed that the displacements are decreasing with the increase in number of reinforcement layers while acceleration amplifications are not affected significantly.

A Simulation Based Study and Analysis of Double Gate Tunnel FET Performance for Low Stand-By Power Applications

The conventional metal oxide semiconductor field effect transistor (MOSFET)may not be suitable for future low standby power (LSTP) applications due to its high off-state current as the sub-threshold swing is theoretically limited to 60mV/decade. Tunnel field effect transistor (TFET) based on gate controlled band to band tunneling has attracted attention for such applications due to its extremely small sub-threshold swing (much less than 60mV/decade). This paper takes a simulation approach to gain some insight into its electrostatics and the carrier transport mechanism. Using 2D device simulations, a thorough study and analysis of the electrical parameters of the planar double gate TFET is performed. Due to excellent sub-threshold characteristics and a reverse biased structure, it offers orders of magnitude less leakage current compared to the conventional MOSFET. In this work, it is shown that the device can be scaled down to channel lengths as small as 30 nm without affecting its performance. Also, it is observed that the bulk region of the device plays a major role in determining the sub-threshold characteristics of the device and considerable improvement in performance (in terms of ION/IOFF ratio) can be achieved if the thickness of the device is reduced. An ION/IOFF ratio of 2x1012 and a minimum point sub-threshold swing of 22mV/decade is obtained.

Influence of Gate Corrugations on the Performance of Thin-Film Transistors

This letter investigates the influence of a corrugated gate on the transfer characteristics of thin-film transistors. Corrugations that run parallel to the length of the channel from source to drain are patterned on the gate. The author finds that these corrugations result in higher currents as compared to conventional planar-gate transistors.

Low threshold voltage ZnO thin film transistor with a Zn0.7Mg0.3O gate dielectric for transparent electronics

A highly transparent all ZnO thin film transistor (ZnO-TFT) with a transmittance of above 80% in the visible part of the spectrum, was fabricated by direct current magnetron sputtering, with a bottom gate configuration. The ZnO-TFT with undoped ZnO channel layers deposited on 300 nm Zn0.7Mg0.3O gate dielectric layers attains an on/off ratio of 104 and mobility of 20 cm2/V s. The capacitance-voltage (C−V) characteristics of the ZnO-TFT exhibited a transition from depletion to accumulation with a small hysteresis indicating the presence of oxide traps. The trap density was also computed from the Levinson’s plot. The use of Zn0.7Mg0.3O as a dielectric layer adds additional dimension to its applications. The room temperature processing of the device depicts the possibility of the use of flexible substrates such as polymer substrates. The results provide the realization of transparent electronics for next-generation optoelectronics.

Effect of gate-drain/source overlap on the noise in 90 nm N-channel metal oxide semiconductor field effect transistors

In this paper, we have studied the effect of gate-drain/source overlap (LOV) on the drain channel noise and induced gate current noise (SIg) in 90 nm N-channel metal oxide semiconductor field effect transistors using process and device simulations. As the change in overlap affects the gate tunneling leakage current, its effect on shot noise component of SIg has been taken into consideration. It has been shown that “control over LOV” allows us to get better noise performance from the device, i.e., it allows us to reduce noise figure, for a given leakage current constraint. LOV in the range of 0–10 nm is recommended for the 90 nm gate length transistors, in order to get the best performance in radio frequency applications.

Characteristics of j.f.e.t.s. taking the separation of gate electrode from the source and drain electrodes into account

The performance characteristics of a junction field-effect transistor (j.f.e.t.) are evaluated considering the presence of the gap between the gate electrode and the source and drain terminals. It is concluded that the effect of the gap is to demand a higher drain voltage to maintain the same drain current. So long as the device is operated at the same drain current, the presence of the gap does not change the performance of the device as an amplifier. The nature of the performance of the device as a variable resistor is not affected by the gap if it is less than or equal to the physical height of the channel. For gap lengths larger than the channel height, the effect of the gap is to add a series resistance in the drain.

Gate Drive Card for High Power Three Phase PWM Converters

Gate driver is an integral part of every power converter, drives the power semiconductor devices and also provides protection for the switches against short-circuit events and over-voltages during shut down. Gate drive card for IGBTs and MOSFETs with basic features can be designed easily by making use of discrete electronic components. Gate driver ICs provides attractive features in a single package, which improves reliability and reduces effort of design engineers. Either case needs one or more isolated power supplies to drive each power semiconductor devices and provide isolation to the control circuitry from the power circuit. The primary emphasis is then to provide simplified and compact isolated power supplies to the gate drive card with the requisite isolation strength and which consumes less space, and for providing thermal protection to the power semiconductor modules for 3-� 3 wire or 4 wire inverters.

A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry

Surface-potential-based compact charge models for symmetric double-gate metal-oxide-semiconductor field-effect transistors (SDG-MOSFETs) are based on the fundamental assumption of having equal oxide thicknesses for both gates. However, for practical devices, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. In this paper, we propose a simple surface-potential-based charge model, which is applicable for tied double-gate MOSFETs having same gate work function but could have any difference in gate oxide thickness. The proposed model utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and thus, it could be implemented in any circuit simulator very easily and extendable to short-channel devices. We also propose a simple physics-based perturbation technique by which the surface potentials of an asymmetric device could be obtained just by solving the input voltage equation of SDG devices for small asymmetry cases. The proposed model, which shows excellent agreement with numerical and TCAD simulations, is implemented in a professional circuit simulator through the Verilog-A interface and demonstrated for a 101-stage ring oscillator simulation. It is also shown that the proposed model preserves the source/drain symmetry, which is essential for RF circuit design.

Inclusion of body doping in compact models for fully-depleted common double gate MOSFET adapted to gate-oxide thickness asymmetry

Since it is difficult to find the analytical solution of the governing Poisson equation for double gate MOSFETs with the body doping term included, the majority of the compact models are developed for undoped-body devices for which the analytical solution is available. Proposed is a simple technique to included a body doping term in such surface potential based common double gate MOSFET models also by taking into account any differences between the gate oxide thickness. The proposed technique is validated against TCAD simulation and found to be accurate as long as the channel is fully depleted.