Extending lagrange interpolation to develop a 4-node quadrilateral element

Today finite element method is a well established tool in engineering analysis and design. Though there axe many two and three dimensional finite elements available, it is rare that a single element performs satisfactorily in majority of practical problems. The present work deals with the development of 4-node quadrilateral element using extended Lagrange interpolation functions. The classical univariate Lagrange interpolation is well developed for 1-D and is used for obtaining shape functions. We propose a new approach to extend the Lagrange interpolation to several variables. When variables axe more than one the method also gives the set of feasible bubble functions. We use the two to generate shape function for the 4-node arbitrary quadrilateral. It will require the incorporation of the condition of rigid body motion, constant strain and Navier equation by imposing necessary constraints. The procedure obviates the need for isoparametric transformation since interpolation functions are generated for arbitrary quadrilateral shapes. While generating the element stiffness matrix, integration can be carried out to the accuracy desired by dividing the quadrilateral into triangles. To validate the performance of the element which we call EXLQUAD4, we conduct several pathological tests available in the literature. EXLQUAD4 predicts both stresses and displacements accurately at every point in the element in all the constant stress fields. In tests involving higher order stress fields the element is assured to converge in the limit of discretisation. A method thus becomes available to generate shape functions directly for arbitrary quadrilateral. The method is applicable also for hexahedra. The approach should find use for development of finite elements for use with other field equations also.

Novel composite coded pattern for small angle measurement using imaging method -art.no.62891D

A novel approach for measurement of small rotation angles using imaging method is proposed and demonstrated. A plane mirror placed on a precision rotating table is used for imaging the newly designed composite coded pattern. The imaged patterns are captured with the help of a CCD camera. The angular rotation of the plane mirror is determined from a pair of the images of the pattern, captured once before and once after affecting the tilt of the mirror. Both simulation and experimental results suggest that the proposed approach not only retains the advantages of the original imaging method but also contributes significantly to the enhancement of its measuring range (+/- 4.13 degrees with accuracy of the order of 1 arcsec).

mRegistry: a registry representation for fault diagnosis

Microsoft Windows uses the notion of registry to store all configuration information. The registry entries have associations and dependencies. For example, the paths to executables may be relative to some home directories. The registry being designed with faster access as one of the objectives does not explicitly capture these relations. In this paper, we explore a representation that captures the dependencies more explicitly using shared and unifying variables. This representation, called mRegistry exploits the tree-structured hierarchical nature of the registry, is concept-based and obtained in multiple stages. mRegistry captures intra-block, inter-block and ancestor-children dependencies (all leaf entries of a parent key in a registry put together as an entity constitute a block thereby making the block as the only child of the parent). In addition, it learns the generalized concepts of dependencies in the form of rules. We show that mRegistry has several applications: fault diagnosis, prediction, comparison, compression etc.

SOI strip waveguide microring resonator for homogeneous biosensing

We report the simulation and analytical results obtained for homogenous or bulk sensing of protein on Siliconon- insulator strip waveguide based microring resonator. The radii of the rings considered are 5 μm and 20 μm; the waveguide dimensions are 300 × 300 nm. A gap of (i) 200 nm and (ii) 300 nm exists between the ring and the bus waveguide. The biomaterial is uniformly distributed over a thickness which exceeds the evanescent field penetration depth of 150 nm. The sensitivities of the resonators are 32.5 nm/RIU and 17.5 nm/RIU (RIU - Refractive index unit) respectively.

SpecNet: Spectrum Sensing Sans Frontieres

While the under-utilization of licensed spectrum based on measurement studies conducted in a few developed countries has spurred lots of interest in opportunistic spectrum access, there exists no infrastructure today for measuring real-time spectrum occupancy across vast geographical regions. In this paper, we present the design and implementation of SpecNet, a first-of-its-kind platform that allows spectrum analyzers around the world to be networked and efficiently used in a coordinated manner for spectrum measurement as well as implementa- tion and evaluation of distributed sensing applications. We demonstrate the value of SpecNet through three applications: 1) remote spectrum measurement, 2) primary transmitter coverage estimation and 3) Spectrum-Cop that quickly identifies and localizes transmitters in a frequency range and geographic region of interest.

Performance Evaluation of Underground Mine Communication and Monitoring Devices: Case Studies

Communication and environmental monitoring play a major role in underground mining both from production and safety point of view. However, underground mining communication as well as monitoring devices encounter several challenges because of the nature of underground features and characteristics. Lack of real time information from underground workings may hamper production and create serious safety risks. Proper communication and monitoring devices are inevitable requirements for better production and improved safety. Communication and environmental monitoring devices are basic element of underground mine infrastructure. This paper describes the performance of communication and monitoring devices being used in underground mines. An attempt has been made to assess the safety risks by these devices which may dictate future research directions.

A systematic design of high-rate full-diversity space-frequency codes for MIMO-OFDM systems

This paper presents a systematic construction of high-rate and full-diversity space-frequency block codes for MIMO-OFDM systems. While all prior constructions offer only a maximum rate of one complex symbol per channel use, our construction yields rate equal to the number of transmit antennas and simultaneously achieves full-diversity. The proposed construction works for arbitrary number of transmit antennas and arbitrary channel power delay profile. A key step in this construction is the generalization of the stacked matrix code design criteria given by Bolcskei et.al., (IEEE WCNC 2000). Explicit equivalence of our generalized code design criteria with the Hadamard-product based criteria of W. Su et.al., (lEEE Trans. Sig. Proc. Nov 2003) is established and new high-rate codes are constructed using our criteria.

An algebraic algorithm for the design and analysis of linear dynamical systems

In an earlier paper [1], it has been shown that velocity ratio, defined with reference to the analogous circuit, is a basic parameter in the complete analysis of a linear one-dimensional dynamical system. In this paper it is shown that the terms constituting velocity ratio can be readily determined by means of an algebraic algorithm developed from a heuristic study of the process of transfer matrix multiplication. The algorithm permits the set of most significant terms at a particular frequency of interest to be identified from a knowledge of the relative magnitudes of the impedances of the constituent elements of a proposed configuration. This feature makes the algorithm a potential tool in a first approach to a rational design of a complex dynamical filter. This algorithm is particularly suited for the desk analysis of a medium size system with lumped as well as distributed elements.

MAC design for heterogeneous application support in OFDM based wireless systems

With the increasing adoption of wireless technology, it is reasonable to expect an increase in file demand for supporting both real-time multimedia and high rate reliable data services. Next generation wireless systems employ Orthogonal Frequency Division Multiplexing (OFDM) physical layer owing, to the high data rate transmissions that are possible without increase in bandwidth. Towards improving file performance of these systems, we look at the design of resource allocation algorithms at medium-access layer, and their impact on higher layers. While TCP-based clastic traffic needs reliable transport, UDP-based real-time applications have stringent delay and rate requirements. The MAC algorithms while catering to the heterogeneous service needs of these higher layers, tradeoff between maximizing the system capacity and providing fairness among users. The novelly of this work is the proposal of various channel-aware resource allocation algorithms at the MAC layer. which call result in significant performance gains in an OFDM based wireless system.

High performance VLSI architecture design for H.264 CAVLC decoder

H.264 video standard achieves high quality video along with high data compression when compared to other existing video standards. H.264 uses context-based adaptive variable length coding (CAVLC) to code residual data in Baseline profile. In this paper we describe a novel architecture for CAVLC decoder including coeff-token decoder, level decoder total-zeros decoder and run-before decoder UMC library in 0.13 mu CMOS technology is used to synthesize the proposed design. The proposed design reduces chip area and improves critical path performance of CAVLC decoder in comparison with [1]. Macroblock level (including luma and chroma) pipeline processing for CAVLC is implemented with an average of 141 cycles (including pipeline buffering) per macroblock at 250MHz clock frequency. To compare our results with [1] clock frequency is constrained to 125MHz. The area required for the proposed architecture is 17586 gates, which is 22.1% improvement in comparison to [1]. We obtain a throughput of 1.73 * 10(6) macroblocks/second, which is 28% higher than that reported in [1]. The proposed design meets the processing requirement of 1080HD [5] video at 30frames/seconds.

Power System Stabilizers Design for Interconnected Power Systems

This paper proposes a method of designing fixed parameter decentralized power system stabilizers (PSS) for interconnected multi-machine power systems. Conventional design technique using a single machine infinite bus approximation involves the frequency response estimation called the GEP(s) between the AVR input and the resultant electrical torque. This requires the knowledge of equivalent external reactance and infinite bus voltage or their estimated values at each machine. Other design techniques using P-Vr characteristics or residues are based on complete system information. In the proposed method, information available at the high voltage bus of the step-up transformer is used to set up a modified Heffron-Phillip's model. With this model it is possible to decide the structure of the PSS compensator and tune its parameters at each machine in the multi-machine environment, using only those signals that are available at the generating station. The efficacy of the proposed design technique has been evaluated on three of the most widely used test systems. The simulation results have shown that the performance of the proposed stabilizer is comparable to that which could be obtained by conventional design but without the need for the estimation and computation of external system parameters.

Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology

Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuit/system. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining, lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL), modeled after CPL, to achieve equal delay along all the propagation paths in the logic structure. An 8×8 b multiplier is designed using this logic in a 0.8 ?m technology. The carry-save multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm×0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well