Minimizing total weighted tardiness on heterogeneous batch processors with incompatible job families

In this paper, we address a scheduling problem for minimizing total weighted tardiness. The background for the paper is derived from the automobile gear manufacturing process. We consider the bottleneck operation of heat treatment stage of gear manufacturing. Real-life scenarios like unequal release times, incompatible job families, nonidentical job sizes, heterogeneous batch processors, and allowance for job splitting have been considered. We have developed a mathematical model which takes into account dynamic starting conditions. The problem considered in this study is NP-hard in nature, and hence heuristic algorithms have been proposed to address it. For real-life large-size problems, the performance of the proposed heuristic algorithms is evaluated using the method of estimated optimal solution available in literature. Extensive computational analyses reveal that the proposed heuristic algorithms are capable of consistently obtaining near-optimal statistically estimated solutions in very reasonable computational time.

Toward a Scalable Working Set Size Estimation Method and Its Application for Chip Multiprocessors

It is essential to accurately estimate the working set size (WSS) of an application for various optimizations such as to partition cache among virtual machines or reduce leakage power dissipated in an over-allocated cache by switching it OFF. However, the state-of-the-art heuristics such as average memory access latency (AMAL) or cache miss ratio (CMR) are poorly correlated to the WSS of an application due to 1) over-sized caches and 2) their dispersed nature. Past studies focus on estimating WSS of an application executing on a uniprocessor platform. Estimating the same for a chip multiprocessor (CMP) with a large dispersed cache is challenging due to the presence of concurrently executing threads/processes. Hence, we propose a scalable, highly accurate method to estimate WSS of an application. We call this method ``tagged WSS (TWSS)'' estimation method. We demonstrate the use of TWSS to switch-OFF the over-allocated cache ways in Static and Dynamic NonUniform Cache Architectures (SNUCA, DNUCA) on a tiled CMP. In our implementation of adaptable way SNUCA and DNUCA caches, decision of altering associativity is taken by each L2 controller. Hence, this approach scales better with the number of cores present on a CMP. It gives overall (geometric mean) 26% and 19% higher energy-delay product savings compared to AMAL and CMR heuristics on SNUCA, respectively.

Electronic Structure of CH3NH3PbX3 Perovskites: Dependence on the Halide Moiety

A combination of measurements using photoelectron spectroscopy and calculations using density functional theory (DFT) was applied to compare the detailed electronic structure of the organolead halide perovskites CH3NH3PbI3 and CH3NH3PbBr3. These perovskite materials are used to absorb light in mesoscopic and planar heterojunction solar cells. The Pb 4f core level is investigated to get insight into the chemistry of the two materials. Valence level measurments are also included showing a shift of the valence band edges where there is a higher binding energy of the edge for the CH3NH3PbBr3 perovskite. These changes are supported by the theoretical calculations which indicate that the differences in electronic structure are mainly caused by the nature of the halide ion rather than structural differences. The combination of photoelectron spectroscopy measurements and electronic structure calculations is essential to disentangle how the valence band edge in organolead halide perovskites is governed by the intrinsic difference in energy levels of the halide ions from the influence of chemical bonding.