Determining optimum subband edges for signal compression

The coding gain in subband coding, a popular technique for achieving signal compression, depends on how the input signal spectrum is decomposed into subbands. The optimality of such decomposition is conventionally addressed by designing appropriate filter banks. The issue of optimal decomposition of the input spectrum is addressed by choosing the set of band that, for a given number of bands, will achieve maximum coding gain. A set of necessary conditions for such optimality is derived, and an algorithm to determine the optimal band edges is then proposed. These band edges along with ideal filters, achieve the upper bound of coding gain for a given number of bands. It is shown that with ideal filters, as well as with realizable filters for some given effective length, such a decomposition system performs better than the conventional nonuniform binary tree-structured decomposition in some cases for AR sources as well as images

On-Chip Memory Architecture Exploration Framework for DSP Processor-Based Embedded System on Chip

Today's SoCs are complex designs with multiple embedded processors, memory subsystems, and application specific peripherals. The memory architecture of embedded SoCs strongly influences the power and performance of the entire system. Further, the memory subsystem constitutes a major part (typically up to 70%) of the silicon area for the current day SoC. In this article, we address the on-chip memory architecture exploration for DSP processors which are organized as multiple memory banks, where banks can be single/dual ported with non-uniform bank sizes. In this paper we propose two different methods for physical memory architecture exploration and identify the strengths and applicability of these methods in a systematic way. Both methods address the memory architecture exploration for a given target application by considering the application's data access characteristics and generates a set of Pareto-optimal design points that are interesting from a power, performance and VLSI area perspective. To the best of our knowledge, this is the first comprehensive work on memory space exploration at physical memory level that integrates data layout and memory exploration to address the system objectives from both hardware design and application software development perspective. Further we propose an automatic framework that explores the design space identifying 100's of Pareto-optimal design points within a few hours of running on a standard desktop configuration.

Applying Genetic Algorithms to Optimize Power in Tiled SNUCA Chip Multicore Architectures

We propose a novel technique for reducing the power consumed by the on-chip cache in SNUCA chip multicore platform. This is achieved by what we call a "remap table", which maps accesses to the cache banks that are as close as possible to the cores, on which the processes are scheduled. With this technique, instead of using all the available cache, we use a portion of the cache and allocate lesser cache to the application. We formulate the problem as an energy-delay (ED) minimization problem and solve it offline using a scalable genetic algorithm approach. Our experiments show up to 40% of savings in the memory sub-system power consumption and 47% savings in energy-delay product (ED).

Applying Genetic Algorithms to Optimize Power in Tiled SNUCA Chip Multicore Architectures

We propose a novel technique for reducing the power consumed by the on-chip cache in SNUCA chip multicore platform. This is achieved by what we call a "remap table", which maps accesses to the cache banks that are as close as possible to the cores, on which the processes are scheduled. With this technique, instead of using all the available cache, we use a portion of the cache and allocate lesser cache to the application. We formulate the problem as an energy-delay (ED) minimization problem and solve it offline using a scalable genetic algorithm approach. Our experiments show up to 40% of savings in the memory sub-system power consumption and 47% savings in energy-delay product (ED).

Adaptive power optimization of on-chip SNUCA cache on tiled chip multicore architecture using remap policy

Advances in technology have increased the number of cores and size of caches present on chip multicore platforms(CMPs). As a result, leakage power consumption of on-chip caches has already become a major power consuming component of the memory subsystem. We propose to reduce leakage power consumption in static nonuniform cache architecture(SNUCA) on a tiled CMP by dynamically varying the number of cache slices used and switching off unused cache slices. A cache slice in a tile includes all cache banks present in that tile. Switched-off cache slices are remapped considering the communication costs to reduce cache usage with minimal impact on execution time. This saves leakage power consumption in switched-off L2 cache slices. On an average, there map policy achieves 41% and 49% higher EDP savings compared to static and dynamic NUCA (DNUCA) cache policies on a scalable tiled CMP, respectively.

Design and Application of a new Multiscale Multidirectional Non-subsampled Filter Bank

We propose a new method for design of computationally efficient nonsubsampled multiscale multidirectional filter bank with perfect reconstruction (PR). This filter bank is composed of two nonsubsampled filter banks, for multiscale decomposition and for directional expansion. For multiscale decomposition, we transform the 1-D equivalent subband filters directly into 2-D equivalent subband filters. The computational cost is considerably reduced by avoiding the computation of 2-D convolutions. The multidirectional decomposition utilizes fan filters. A new method for design of 2-D zero phase FIR fan filter transformation function is developed. This method also aids the transformation of a 1-D filter bank to a 2-D multidirectional filter bank. The potential application of the proposed filter bank is illustrated by comparing the image denoising performance of the proposed filter bank with other design method that exist in available literature.

Black hole formation in fuzzy sphere collapse

We study the collapse of a fuzzy sphere, that is a spherical membrane built out of D0-branes, in the Banks-Fischler-Shenker-Susskind model. At weak coupling, as the sphere shrinks, open strings are produced. If the initial radius is large then open string production is not important and the sphere behaves classically. At intermediate initial radius the backreaction from open string production is important but the fuzzy sphere retains its identity. At small initial radius the sphere collapses to form a black hole. The crossover between the later two regimes is smooth and occurs at the correspondence point of Horowitz and Polchinski.

Identifying services from Legacy batch applications

Transaction processing is a key constituent of the IT workload of commercial enterprises (e.g., banks, insurance companies). Even today, in many large enterprises, transaction processing is done by legacy "batch" applications, which run offline and process accumulated transactions. Developers acknowledge the presence of multiple loosely coupled pieces of functionality within individual applications. Identifying such pieces of functionality (which we call "services") is desirable for the maintenance and evolution of these legacy applications. This is a hard problem, which enterprises grapple with, and one without satisfactory automated solutions. In this paper, we propose a novel static-analysis-based solution to the problem of identifying services within transaction-processing programs. We provide a formal characterization of services in terms of control-flow and data-flow properties, which is well-suited to the idioms commonly exhibited by business applications. Our technique combines program slicing with the detection of conditional code regions to identify services in accordance with our characterization. A preliminary evaluation, based on a manual analysis of three real business programs, indicates that our approach can be effective in identifying useful services from batch applications.

Gammatone Wavelet Cepstral Coefficients for Robust Speech Recognition

We develop noise robust features using Gammatone wavelets derived from the popular Gammatone functions. These wavelets incorporate the characteristics of human peripheral auditory systems, in particular the spatially-varying frequency response of the basilar membrane. We refer to the new features as Gammatone Wavelet Cepstral Coefficients (GWCC). The procedure involved in extracting GWCC from a speech signal is similar to that of the conventional Mel-Frequency Cepstral Coefficients (MFCC) technique, with the difference being in the type of filterbank used. We replace the conventional mel filterbank in MFCC with a Gammatone wavelet filterbank, which we construct using Gammatone wavelets. We also explore the effect of Gammatone filterbank based features (Gammatone Cepstral Coefficients (GCC)) for robust speech recognition. On AURORA 2 database, a comparison of GWCCs and GCCs with MFCCs shows that Gammatone based features yield a better recognition performance at low SNRs.