Design and analysis of rate aware ad hoc 802.11 networks

802.11 WLANs are characterized by high bit error rate and frequent changes in network topology. The key feature that distinguishes WLANs from wired networks is the multi-rate transmission capability, which helps to accommodate a wide range of channel conditions. This has a significant impact on higher layers such as routing and transport levels. While many WLAN products provide rate control at the hardware level to adapt to the channel conditions, some chipsets like Atheros do not have support for automatic rate control. We first present a design and implementation of an FER-based automatic rate control state machine, which utilizes the statistics available at the device driver to find the optimal rate. The results show that the proposed rate switching mechanism adapts quite fast to the channel conditions. The hop count metric used by current routing protocols has proven itself for single rate networks. But it fails to take into account other important factors in a multi-rate network environment. We propose transmission time as a better path quality metric to guide routing decisions. It incorporates the effects of contention for the channel, the air time to send the data and the asymmetry of links. In this paper, we present a new design for a multi-rate mechanism as well as a new routing metric that is responsive to the rate. We address the issues involved in using transmission time as a metric and presents a comparison of the performance of different metrics for dynamic routing.

Design and fabrication of an automated temperature programmed reaction system to evaluate 3-way catalysts Ce1-x-y(La/Y)(x)PtyO2-delta

A completely automated temperature-programmed reaction (TPR) system for carrying out gas-solid catalytic reactions under atmospheric flow conditions is fabricated to study CO and hydrocarbon oxidation, and NO reduction. The system consists of an all-stainless steel UHV system, quadrupole mass spectrometer SX200 (VG Scientific), a tubular furnace and micro-reactor, a temperature controller, a versatile gas handling system, and a data acquisition and analysis system. The performance of the system has been tested under standard experimental conditions for CO oxidation over well-characterized Ce1-x-y(La/Y)(y)O2-delta catalysts. Testing of 3-way catalysis with CO, NO and C2H2 to convert to CO2, N-2 and H2O is done with this catalyst which shows complete removal of pollutants below 325 degrees C. Fixed oxide-ion defects in Pt substituted Ce1-y(La/Y)(y)O2-y/2 show higher catalytic activity than Pt ion-substituted CeO2

Design and performance evaluation of a systolic architecture for hidden-surface removal

In this paper, we propose a systolic architecture for hidden-surface removal. Systolic architecture is a kind of parallel architecture best known for its easy VLSI implementability. After discussing the design details of the architecture, we present the results of the simulation experiments conducted in order to evaluate the performance of the architecture.

Design and fabrication of an automated temperature programmed reaction system to evaluate 3-way catalysts Ce1-x-y(La/Y)(x)PtyO2-delta

A completely automated temperature-programmed reaction (TPR) system for carrying out gas-solid catalytic reactions under atmospheric flow conditions is fabricated to study CO and hydrocarbon oxidation, and NO reduction. The system consists of an all-stainless steel UHV system, quadrupole mass spectrometer SX200 (VG Scientific), a tubular furnace and micro-reactor, a temperature controller, a versatile gas handling system, and a data acquisition and analysis system. The performance of the system has been tested under standard experimental conditions for CO oxidation over well-characterized Ce1-x-y(La/Y)(y)O2-delta catalysts. Testing of 3-way catalysis with CO, NO and C2H2 to convert to CO2, N-2 and H2O is done with this catalyst which shows complete removal of pollutants below 325 degrees C. Fixed oxide-ion defects in Pt substituted Ce1-y(La/Y)(y)O2-y/2 show higher catalytic activity than Pt ion-substituted CeO2.

Design and fabrication of an indigenous molecular beam ultraviolet photoelectron spectrometer

An ultraviolet photoelectron spectrometer for the study of van der Waals molecules has been designed and fabricated indigenously. The spectrometer consists of an HeI discharge lamp, a molecular beam sample inlet system, an electrostatic lens, a 180-degrees hemispherical electrostatic analyser and a channeltron detector. Performance of the spectrometer is illustrated with an example.

Modelling, Design and Analysis of Low Frequency Platform for Attenuating Micro-Vibration in Spacecraft

One of the most important factors that affect the pointing of precision payloads and devices in space platforms is the vibration generated due to static and dynamic unbalanced forces of rotary equipments placed in the neighborhood of payload. Generally, such disturbances are of low amplitude, less than 1 kHz, and are termed as ‘micro-vibrations’. Due to low damping in the space structure, these vibrations have long decay time and they degrade the performance of payload. This paper addresses the design, modeling and analysis of a low frequency space frame platform for passive and active attenuation of micro-vibrations. This flexible platform has been designed to act as a mount for devices like reaction wheels, and consists of four folded continuous beams arranged in three dimensions. Frequency and response analysis have been carried out by varying the number of folds, and thickness of vertical beam. Results show that lower frequencies can be achieved by increasing the number of folds and by decreasing the thickness of the blade. In addition, active vibration control is studied by incorporating piezoelectric actuators and sensors in the dynamic model. It is shown using simulation that a control strategy using optimal control is effective for vibration suppression under a wide variety of loading conditions.

Design and fabrication of an automated thermal desorption gas-solid reaction system: Oxidation of ammonia and methanol over YBa2Cu3O7−δ(123) oxide systems

A fully automated, versatile Temperature Programmed Desorption (TDP), Temperature Programmed Reaction (TPR) and Evolved Gas Analysis (EGA) system has been designed and fabricated. The system consists of a micro-reactor which can be evacuated to 10−6 torr and can be heated from 30 to 750°C at a rate of 5 to 30°C per minute. The gas evolved from the reactor is analysed by a quadrupole mass spectrometer (1–300 amu). Data on each of the mass scans and the temperature at a given time are acquired by a PC/AT system to generate thermograms. The functioning of the system is exemplified by the temperature programmed desorption (TPD) of oxygen from YBa2Cu3−xCoxO7 ± δ, catalytic ammonia oxidation to NO over YBa2Cu3O7−δ and anaerobic oxidation of methanol to CO2, CO and H2O over YBa2Cu3O7−δ (Y123) and PrBa2Cu3O7−δ (Pr123) systems.

Control of lipid microstructures by molecular design and its implications

An overview of the current trends in the lipid design for specific applications has been presented. Lipids with different surface charge and hydrophobic backbone undergo aggregation to produce lamellae or bilayer and multilayer vesicles in aqueous media. Various aspects of present development of chiral superstructures and enzyme-mimics have been discussed. Utility of these molecules for potential applications in immunomodulation and sustained drug-delivery systems is also summarized.

Design and development of a self-supported polymer electrolyte fuel cell system with anodic dead-end operation

Design and operational details for a self-supported polymer electrolyte fuel cell (PEFC) system with anodic dead-end fuel supply and internally humidified cathodic oxidant flow are described. During the PEFC operation, nitrogen and water back diffuse across the Nafion membrane from the cathode to the anode and accumulate in the anode flow channels affecting stack performance. The accumulated inert species are flushed from the stack by purging the fuel cell stack with a timer-activated purge valve to address the aforesaid problem. To minimize the system complexity, stack is designed in such a way that all the inert species accumulate in only one cell called the purge cell. A pulsed purge sequence comprises opening the valve for purge duration followed by purge-valve closing for the hold period and repeating the sequence in cycles. Since self-humidification is inadequate to keep the membrane wet, the anodic dead-end-operated PEFC stack with composite membrane comprising perflourosulphonic acid (Nafion) and silica is employed for keeping the membrane humidified even while operating the stack with dry hydrogen and internally humidified air.

Design and implementation of a PC-based FPGA tester

A new range of programmable logic devices are revolutionizing the way complex digital hardware is designed and built all over the world. Being able to test these devices in order to validate and dynamically improve on the design is crucial. This paper describes a low-cost FPGA tester that can test SRAM based FPGAs in the laboratory.

Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology

Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuit/system. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining, lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL), modeled after CPL, to achieve equal delay along all the propagation paths in the logic structure. An 8×8 b multiplier is designed using this logic in a 0.8 ?m technology. The carry-save multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm×0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well

Design and synthesis of new bile acid-based macrocycles

A strategy for the synthesis of new macrocycles built on 7-deoxycholic acid is described.