{C}^0$ penalty methods for the fully nonlinear Monge-Ampère equation

In this paper, we develop and analyze C(0) penalty methods for the fully nonlinear Monge-Ampere equation det(D(2)u) = f in two dimensions. The key idea in designing our methods is to build discretizations such that the resulting discrete linearizations are symmetric, stable, and consistent with the continuous linearization. We are then able to show the well-posedness of the penalty method as well as quasi-optimal error estimates using the Banach fixed-point theorem as our main tool. Numerical experiments are presented which support the theoretical results.

Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor

A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.

Towards formal verification of analog mixed signal designs using SPICE circuit simulation traces

An extension to a formal verification approach of hybrid systems is proposed to verify analog and mixed signal (AMS) designs. AMS designs can be formally modeled as hybrid systems and therefore lend themselves to the formal analysis and verification techniques applied to hybrid systems. The proposed approach employs simulation traces obtained from an actual design implementation of AMS circuit blocks (for example, in the form of SPICE netlists) to carry out formal analysis and verification. This enables the same platform used for formally validating an abstract model of an AMS design, to be also used for validating its different refinements and design implementation; thereby, providing a simple route to formal verification at different levels of implementation. The feasibility of the proposed approach is demonstrated with a case study based on a tunnel diode oscillator. Since the device characteristic of a tunnel diode is highly non-linear with a negative resistance region, dynamic behavior of circuits in which it is employed as an element is difficult to model, analyze and verify within a general hybrid system formal verification tool. In the case study presented the formal model and the proposed computational techniques have been incorporated into CheckMate, a formal verification tool based on MATLAB and Simulink-Stateflow Framework from MathWorks.

Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor

A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.

Badly approximable numbers and vectors in Cantor-like sets

We show that a large class of Cantor-like sets of R-d, d >= 1, contains uncountably many badly approximable numbers, respectively badly approximable vectors, when d >= 2. An analogous result is also proved for subsets of R-d arising in the study of geodesic flows corresponding to (d+1)-dimensional manifolds of constant negative curvature and finite volume, generalizing the set of badly approximable numbers in R. Furthermore, we describe a condition on sets, which is fulfilled by a large class, ensuring a large intersection with these Cantor-like sets.

Functions for rice RFL in vegetative axillary meristem specification and outgrowth

Roles for the transcription factor RFL in rice axillary meristem development were studied. Its regulatory effects on LAX1, CUC1, and OsPIN3 reveal its functions in axillary meristem specification and outgrowth.Axillary meristems (AMs) are secondary shoot meristems whose outgrowth determines plant architecture. In rice, AMs form tillers, and tillering mutants reveal an interplay between transcription factors and the phytohormones auxin and strigolactone as some factors that underpin this developmental process. Previous studies showed that knockdown of the transcription factor gene RFL reduced tillering and caused a very large decrease in panicle branching. Here, the relationship between RFL, AM initiation, and outgrowth was examined. We show that RFL promotes AM specification through its effects on LAX1 and CUC genes, as their expression was modulated on RFL knockdown, on induction of RFL:GR fusion protein, and by a repressive RFL-EAR fusion protein. Further, we report reduced expression of auxin transporter genes OsPIN1 and OsPIN3 in the culm of RFL knockdown transgenic plants. Additionally, subtle change in the spatial pattern of IR4 DR5:GFP auxin reporter was observed, which hints at compromised auxin transport on RFL knockdown. The relationship between RFL, strigolactone signalling, and bud outgrowth was studied by transcript analyses and by the tillering phenotype of transgenic plants knocked down for both RFL and D3. These data suggest indirect RFL-strigolactone links that may affect tillering. Further, we show expression modulation of the auxin transporter gene OsPIN3 upon RFL:GR protein induction and by the repressive RFL-EAR protein. These modified forms of RFL had only indirect effects on OsPIN1. Together, we have found that RFL regulates the LAX1 and CUC genes during AM specification, and positively influences the outgrowth of AMs though its effects on auxin transport.