45 resultados para AREA


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This paper deals with the development and performance evaluation of three modified versions of a scheme proposed for medium access control in local area networks. The original scheme implements a collision-free and fair medium arbitration by using a control wire in conjunction with a data bus. The modifications suggested in this paper are intended to realize the multiple priority function in local area networks.

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Large-area PVDF thin films have been prepared and characterized for quasi-static and high frequency dynamic strain sensing applications. These films are prepared using hot press method and the piezoelectric phase (beta-phase) has been achieved by thermo-mechanical treatment and poling under DC field. The fabricated films have been characterized for quasi-static strain sensing and the linear strain-voltage relationship obtained is promising. In order to evaluate the ultrasonic sensing properties, a PZT wafer has been used to launch Lamb waves in a metal beam on which the PVDF film sensor is bonded at a distance. The voltage signals obtained from the PVDF films have been compared with another PZT wafer sensor placed on the opposite surface of the beam as a reference signal. Due to higher stiffness and higher thickness of the PZT wafer sensors, certain resonance patterns significantly degrade the sensor sensitivity curves. Whereas, the present results show that the large-area PVDF sensors can be superior with the signal amplitude comparable to that of PZT sensors and with no resonance-induced effect, which is due to low mechanical impedance, smaller thickness and larger area of the PVDF film. Moreover, the developed PVDF sensors are able to capture both A(0) and S-0 modes of Lamb wave, whereas the PZT sensors captures only A(0) mode in the same scale of voltage output. This shows promises in using large-area PVDF films with various surface patterns on structures for distributed sensing and structural health monitoring under quasi-static, vibration and ultrasonic situations. (C) 2010 Elsevier B.V. All rights reserved.

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High performance video standards use prediction techniques to achieve high picture quality at low bit rates. The type of prediction decides the bit rates and the image quality. Intra Prediction achieves high video quality with significant reduction in bit rate. This paper present an area optimized architecture for Intra prediction, for H.264 decoding at HDTV resolution with a target of achieving 60 fps. The architecture was validated on Virtex-5 FPGA based platform. The architecture achieves a frame rate of 64 fps. The architecture is based on multi-level memory hierarchy to reduce latency and ensure optimum resources utilization. It removes redundancy by reusing same functional blocks across different modes. The proposed architecture uses only 13% of the total LUTs available on the Xilinx FPGA XC5VLX50T.

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Reaction between the various species in slag and metal phase is usually mass transfer controlled. There have been continuous efforts to increase the reaction efficiency in slag-metal system, especially during decarburization of steel to produce the ultra low carbon steel (ULCS) in secondary steelmaking. It has been found that the surface reaction is a dominant factor in the final stage of decarburization. In the initial stage, the inner site reaction is major factor in the refining process. The mixing of bath affects the later reaction. However, the former reaction (surface reaction) is affected by the plume size area at the top of the metal surface. Therefore, a computational study has been made to understand the fluid dynamics of a new secondary steelmaking process called Revolutionary Degasser Activator (REDA) to study the bath mixing and plume area. REDA process has been considered as it is claimed that this process can reduce the carbon content in steel below 10ppm in a less time than the other existing processes such as RH and Tank degasser. This study shows that both bath mixing and plume area are increased in REDA process facilitating it to give the desired carbon content in less time. Qualitative comments are made on slag-metal reaction system based on this finding.

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Studies have been carried out to recover copper from vanadiferrous magnetite ores by a novel reaction with lime in the presence of water vapour. The ore, mixed with different proportions of lime, has been roasted in the presence of steam. The roasted product is either directly leached with dilute mineral acids or subjected to magnetic separation and then leached. The effect of various parameters such as amount of lime added, temperature and duration of roasting and time of leaching on the recovery of copper has been investigated. The results indicate that over 90% copper could be recovered under optimum conditions of roasting and leaching.

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A series of novel, microporous polymer networks (MPNs) have been generated in a simple, acid catalysed Friedel-Crafts-type self-condensation of A(2)B(2)- and A(2)B(4)-type fluorenone monomers. Two A2B4-type monomers with 2,7-bis(N, N-diphenylamino) A or 2,7-bis [4-(N, N-diphenylamino) phenyl] D substitution of the fluorenone cores lead to MPNs with high S(BET) surface areas of up to 1400 m(2) g(-1). Two MPNs made of binary monomer mixtures showed the highest Brunauer-Emmett-Teller (BET) surface areas S(BET) of our series (SBET of up to 1800 m(2) g(-1)) after washing the powdery samples with supercritical carbon dioxide. Total pore volumes of up to 1.6 cm(3) g(-1) have been detected. It is observed that the substitution pattern of the monomers is strongly influencing the resulting physicochemical properties of the microporous polymer networks (MPNs).

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Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters. Hence these models are hard to use directly to make high level microarchitectural trade-offs in the initial exploration phase of a design. In this paper, we propose INTACTE, a tool that can be used by architects toget reasonably accurate interconnect area, delay, and power estimates based on a few architecture level parameters for the interconnect such as length, width (in number of bits), frequency, and latency for a specified technology and voltage. The tool uses well known models of interconnect delay and energy taking into account the wire pitch, repeater size, and spacing for a range of voltages and technologies.It then solves an optimization problem of finding the lowest energy interconnect design in terms of the low level circuit parameters, which meets the architectural constraintsgiven as inputs. In addition, the tool also provides the area, energy, and delay for a range of supply voltages and degrees of pipelining, which can be used for micro-architectural exploration of a chip. The delay and energy models used by the tool have been validated against low level circuit simulations. We discuss several potential applications of the tool and present an example of optimizing interconnect design in the context of clustered VLIW architectures. Copyright 2007 ACM.

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H.264 is a video codec standard which delivers high resolution video even at low bit rates. To provide high throughput at low bit rates hardware implementations are essential. In this paper, we propose hardware implementations for speed and area optimized DCT and quantizer modules. To target above criteria we propose two architectures. First architecture is speed optimized which gives a high throughput and can meet requirements of 4096x2304 frame at 30 frames/sec. Second architecture is area optimized and occupies 2009 LUTs in Altera’s stratix-II and can meet the requirements of 1080HD at 30 frames/sec.

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Chronic recording of neural signals is indispensable in designing efficient brain–machine interfaces and to elucidate human neurophysiology. The advent of multichannel micro-electrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system can vary over time due to change in electrode–neuron distance and background noise. We propose a neural amplifier in UMC 130 nm, 1P8M complementary metal–oxide–semiconductor (CMOS) technology. It can be biased adaptively from 200 nA to 2 $mu{rm A}$, modulating input referred noise from 9.92 $mu{rm V}$ to 3.9 $mu{rm V}$. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier and obviates the need of large input capacitance. The amplifier achieves a noise efficiency factor of 2.58. The amplifier can pass signal from 5 Hz to 7 kHz and the bandwidth of the amplifier can be tuned for rejecting low field potentials (LFP) and power line interference. The amplifier achieves a mid-band voltage gain of 37 dB. In vitro experiments are performed to validate the applicability of the neural low noise amplifier in neural recording systems.

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This paper describes an application of a FACTS supplementary controller for damping of inter area oscillations in power systems. A fuzzy logic controller is designed to regulate a thyristor controlled series capacitor (TCSC) in a multimachine environment to produce additional damping in the system. Simultaneous application of the excitation controller and proposed controller is also investigated. Simulation studies have been done with different types of disturbances and the results are shown to be consistent with the expected performance of the supplementary controller.