Electron mobility in few-layer MoxW1-xS2

Heterostructures of two-dimensional (2D) layered materials are increasingly being explored for electronics in order to potentially extend conventional transistor scaling and to exploit new device designs and architectures. Alloys form a key underpinning of any heterostructure device technology and therefore an understanding of their electronic properties is essential. In this paper, we study the intrinsic electron mobility in few-layer MoxW1-xS2 as limited by various scattering mechanisms. The room temperature, energy-dependent scattering times corresponding to polar longitudinal optical (LO) phonon, alloy and background impurity scattering mechanisms are estimated based on the Born approximation to Fermi's golden rule. The contribution of individual scattering rates is analyzed as a function of 2D electron density as well as of alloy composition in MoxW1-xS2. While impurity scattering limits the mobility for low carrier densities (<2-4x10(12) cm(-2)), LO polar phonon scattering is the dominant mechanism for high electron densities. Alloy scattering is found to play a non-negligible role for 0.5 < x < 0.7 in MoxW1-xS2. The LO phonon-limited and impurity-limited mobilities show opposing trends with respect to alloy mole fractions. The understanding of electron mobility in MoxW1-xS2 presented here is expected to enable the design and realization of heterostructures and devices based on alloys of MoS2 andWS(2).

Curvature Management in Buffer Layer for Device Quality GaN Growth on Si (111)

An efficient buffer layer scheme has been designed to address the issue of curvature management during metalorganic chemical vapour deposition growth of GaN on Si (111) substrate. This is necessary to prevent cracking of the grown layer during post-growth cooling down from growth temperature to room temperature and to achieve an allowable bow (<40 m) in the wafer for carrying out lithographic processes. To meet both these ends simultaneously, the stress evolution in the buffer layers was observed carefully. The reduction in precursor flow during the buffer layer growth provided better control over curvature evolution in the growing buffer layers. This has enabled the growth of a suitable high electron mobility transistor (HEMT) stack on 2'' Si (111) substrate of 300 m thickness with a bow as low as 11.4 m, having a two-dimensional electron gas (2DEG) of mobility, carrier concentration, and sheet resistance values 1510 cm(2)/V-s, 0.96 x 10(13)/cm(2), and 444 /, respectively. Another variation of similar technique resulted in a bow of 23.4 m with 2DEG mobility, carrier concentration, and sheet resistance values 1960 cm(2)/V-s, 0.98 x 10(13)/cm(2), and 325 /, respectively.

Effect of strain rate response and pin diameter on mechanically mixed layer formation and wear mechanisms in a Ti6Al4V-SS316L pair

Three mechanisms operate during wear of materials. These mechanisms include the Strain Rate Response (SRR - effect of strain rate on plastic deformation), Tribo-Chemical Reactions (TCR) and formation of Mechanically Mixed Layers (MML). The present work investigates the effect of these three in context of the formation of MML. For this wear experiments are done on a pin-on-disc machine using Ti64 as the pin and SS316L as the disc. It is seen that apart from the speed and load, which control the SRR and TCR, the diameter of the pin controls the formation of MML, especially at higher speeds.

Low temperature solution processed high-kappa ZrO2 gate dielectrics for nanoelectonics

The high-kappa gate dielectrics, specifically amorphous films offer salient features such as exceptional mechanical flexibility, smooth surfaces and better uniformity associated with low leakage current density. In this work, similar to 35 nm thick amorphous ZrO2 films were deposited on silicon substrate at low temperature (300 degrees C, 1 h) from facile spin-coating method and characterized by various analytical techniques. The X-ray diffraction and X-ray photoelectron spectroscopy reveal the formation of amorphous phase ZrO2, while ellipsometry analysis together with the Atomic Force Microscope suggest the formation of dense film with surface roughness of 1.5 angstrom, respectively. The fabricated films were integrated in metal-oxide-semiconductor (MOS) structures to check the electrical capabilities. The oxide capacitance (C-ox), flat band capacitance (C-FB), flat band voltage (V-FB), dielectric constant (kappa) and oxide trapped charges (Q(ot)) extracted from high frequency (1 MHz) C-V curve are 186 pF, 104 pF, 0.37V, 15 and 2 x 10(-11) C, respectively. The small flat band voltage 0.37V, narrow hysteresis and very little frequency dispersion between 10 kHz-1 MHz suggest an excellent a-ZrO2/Si interface with very less trapped charges in the oxide. The films exhibit a low leakage current density 4.7 x 10(-9)A/cm(2) at 1V. In addition, the charge transport mechanism across the MOSC is analyzed and found to have a strong bias dependence. The space charge limited conduction mechanism is dominant in the high electric field region (1.3-5 V) due to the presence of traps, while the trap-supported tunneling is prevailed in the intermediate region (0.35-1.3 V). Low temperature solution processed ZrO2 thin films obtained are of high quality and find their importance as a potential dielectric layer on Si and polymer based flexible electronics. (C) 2016 Published by Elsevier B.V.