295 resultados para Voltage noise
Resumo:
A three-level common-mode voltage eliminated inverter with single dc supply using flying capacitor inverter and cascaded H-bridge has been proposed in this paper. The three phase space vector polygon formed by this configuration and the polygon formed by the common-mode eliminated states have been discussed. The entire system is simulated in Simulink and the results are experimentally verified. This system has an advantage that if one of devices in the H-bridge fails, the system can still be operated as a normal three-level inverter at full power. This inverter has many other advantages like use of single dc supply, making it possible for a back-to-back grid-tied converter application, improved reliability, etc.
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In this brief, the substrate noise effects of a pulsed clocking scheme on the output spur level, the phase noise, and the peak-to-peak (Pk-Pk) deterministic period jitter of an integer-N charge-pump phase-locked loop (PLL) are demonstrated experimentally. The phenomenon of noise coupling to the PLL is also explained through experiments. The PLL output frequency is 500 MHz and it is implemented in the 0.13-mu m CMOS technology. Measurements show a reduction of 12.53 dB in the PLL output spur level at an offset of 5 MHz and a reduction of 107 ps in the Pk-Pk deterministic period jitter upon reducing the duty cycle of the signal injected into the substrate from 50% to 20%. The results of the analyses suggest that using a pulsed clocking scheme for digital systems in mixed-signal integration along with other isolation techniques helps reduce the substrate noise effects on sensitive analog/radio-frequency circuits.
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This paper presents a new voltage stability index based on the tangent vector of the power flow jacobian. This index is capable of providing the relative vulnerability information of the system buses from the point of view of voltage collapse. In an effort to compare this index with a similar index, the popular voltage stability index L is studied and it is shown through system studies that the L index is not a very consistent indicator of the voltage collapse point of the system but is only a reasonable indicator of the vulnerability of the system buses to voltage collapse. We also show that the new index can be used in the voltage stability analysis of radial systems which is not possible with the L index. This is a significant result of this investigation since there is a lot of contemporary interest in distributed generation and microgrids which are by and large radial in nature. Simulation results considering several test systems are provided to validate the results and the computational needs of the proposed scheme is assessed in comparison with other schemes
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Voltage source inverters are an integral part of renewable power sources and smart grid systems. Computationally efficient and fairly accurate models for the voltage source inverter are required to carry out extensive simulation studies on complex power networks. Accuracy requires that the effect of dead-time be incorporated in the inverter model. The dead-time is essentially a short delay introduced between the gating pulses to the complementary switches in an inverter leg for the safety of power devices. As the modern voltage source inverters switch at fairly high frequencies, the dead-time significantly influences the output fundamental voltage. Dead-time also causes low-frequency harmonic distortion and is hence important from a power quality perspective. This paper studies the dead-time effect in a synchronous dq reference frame, since dynamic studies and controller design are typically carried out in this frame of reference. For the sake of computational efficiency, average models are derived, incorporating the dead-time effect, in both RYB and dq reference frames. The average models are shown to consume less computation time than their corresponding switching models, the accuracies of the models being comparable. The proposed average synchronous reference frame model, including effect of dead-time, is validated through experimental results.
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We present electrical transport arid low frequency (1/f) noise measurements on mechanically exfoliated single, In and triLayer MoS2-based FPI devices on Si/SiO2 substrate. We find that tie electronic states hi MoS2 are localized at low temperatures (T) and conduction happens through variable range hopping (VRH). A steep increase of 1/f noise with decreasing T, typical for localized regime was observed in all of our devices. From gate voltage dependence of noise, we find that the noise power is inversely proportional to square of the number density (proportional to 1/n(2)) for a wide range of T, indicating number density fluctuations to be the dominant source of 1/f noise in these MoS2 FETs.
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We present the study of low-frequency noise, or 1/f noise, in degenerately doped Si: P and Ge: P delta-layers at low temperatures. For the Si: P d-layers we find that the noise is several orders of magnitude lower than that of bulk Si: P systems in the metallic regime and is one of the lowest values reported for doped semiconductors. Ge: P d-layers as a function of perpendicular magnetic field, shows a factor of two reduction in noise magnitude at the scale of B-phi, where B-phi is phase breaking field. We show that this is a characteristic feature of universal conductance fluctuations.
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A colloid supported against gravitational settling by means of an imposed electric field behaves, on average, as if it is at equilibrium in a confining potential T. M. Squires, J. Fluid Mech. 443, 403 (2001)]. We show, however, that the effective Langevin equation for the colloid contains a nonequilibrium noise source, proportional to the field, arising from the thermal motion of dissolved ions. The position fluctuations of the colloid show strong, experimentally testable signatures of nonequilibrium behavior, including a highly anisotropic, frequency-dependent ``effective temperature'' obtained from the fluctuation-dissipation ratio.
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In this paper, a current error space vector (CESV) based hysteresis controller for a 12-sided polygonal voltage space vector inverter fed induction motor (IM) drive is proposed, for the first time. An open-end winding configuration is used for the induction motor. The proposed controller uses parabolic boundary with generalized vector selection logic for all sectors. The drive scheme is first studied with a space vector based PWM (SVPWM) control and from this the current error space phasor boundary is obtained. This current error space phasor boundary is approximated with four parabolas and then the system is run with space phasor based hysteresis PWM controller by limiting the CESV within the parabolic boundary. The proposed controller has increased modulation range, absence of 5th and 7th order harmonics for the entire modulation range, nearly constant switching frequency, fast dynamic response with smooth transition to the over modulation region and a simple controller implementation.
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Current methods for molecular simulations of Electric Double Layer Capacitors (EDLC) have both the electrodes and the electrolyte region in a single simulation box. This necessitates simulation of the electrode-electrolyte region interface. Typical capacitors have macroscopic dimensions where the fraction of the molecules at the electrode-electrolyte region interface is very low. Hence, large systems sizes are needed to minimize the electrode-electrolyte region interfacial effects. To overcome these problems, a new technique based on the Gibbs Ensemble is proposed for simulation of an EDLC. In the proposed technique, each electrode is simulated in a separate simulation box. Application of periodic boundary conditions eliminates the interfacial effects. This in addition to the use of constant voltage ensemble allows for a more convenient comparison of simulation results with experimental measurements on typical EDLCs. (C) 2014 AIP Publishing LLC.
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Non-crystalline semiconductor based thin film transistors are the building blocks of large area electronic systems. These devices experience a threshold voltage shift with time due to prolonged gate bias stress. In this paper we integrate a recursive model for threshold voltage shift with the open source BSIM4V4 model of AIM-Spice. This creates a tool for circuit simulation for TFTs. We demonstrate the integrity of the model using several test cases including display driver circuits.
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Voltage Source Inverter (VSI) fed induction motors are widely used in variable speed applications. For inverters using fixed switching frequency PWM, the output harmonic spectra are located at a few discrete frequencies. The ac motordrives powered by these inverters cause acoustic noise. This paper proposes a new variable switching frequency pwm technique and compares its performance with constant switching frequency pwm technique. It is shown that the proposed technique leads to spread spectra of voltages and currents. Also this technique ensures that no lower order harmonics are present and the current THD is comparable to that of fixed switching frequency PWM and is even better for higher modulation indices.
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Workplace noise has become one of the major issues in industry not only because of workers’ health but also due to safety. Electric motors, particularly, inverter fed induction motors emit objectionably high levels of noise. This has led to the emergence of a research area, concerned with measurement and mitigation of the acoustic noise. This paper presents a lowcost option for measurement and spectral analysis of acoustic noise emitted by electric motors. The system consists of an electret microphone, amplifier and filter. It makes use of the windows sound card and associated software for data acquisition and analysis. The measurement system is calibrated using a professional sound level meter. Acoustic noise measurements are made on an induction motor drive using the proposed system as per relevant international standards. These measurements are seen to match closely with those of a professional meter.
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Information is encoded in neural circuits using both graded and action potentials, converting between them within single neurons and successive processing layers. This conversion is accompanied by information loss and a drop in energy efficiency. We investigate the biophysical causes of this loss of information and efficiency by comparing spiking neuron models, containing stochastic voltage-gated Na+ and K+ channels, with generator potential and graded potential models lacking voltage-gated Na+ channels. We identify three causes of information loss in the generator potential that are the by-product of action potential generation: (1) the voltage-gated Na+ channels necessary for action potential generation increase intrinsic noise and (2) introduce non-linearities, and (3) the finite duration of the action potential creates a `footprint' in the generator potential that obscures incoming signals. These three processes reduce information rates by similar to 50% in generator potentials, to similar to 3 times that of spike trains. Both generator potentials and graded potentials consume almost an order of magnitude less energy per second than spike trains. Because of the lower information rates of generator potentials they are substantially less energy efficient than graded potentials. However, both are an order of magnitude more efficient than spike trains due to the higher energy costs and low information content of spikes, emphasizing that there is a two-fold cost of converting analogue to digital; information loss and cost inflation.