Conversion of plastic waste into CNTs using Ni/Mo/MgO catalystAn optimization approach by mixture experiment

A combustion technique is used to study the synthesis of carbon nano tubes from waste plastic as a precursor and Ni/Mo/MgO as a catalyst. The catalytic activity of three components Ni, Mo, MgO is measured in terms of amount of carbon product obtained. Different proportions of metal ions are optimized using mixture experiment in Design expert software. D-optimal design technique is adopted due to nonsimplex region and presence of constraints in the mixture experiment. The activity of the components is observed to be interdependent and the component Ni is found to be more effective. The catalyst containing Ni0.8Mo0.1MgO0.1 yields more carbon product. The structure of catalyst and CNTs are studied by using SEM, XRD, and Raman spectroscopy. SEM analysis shows the formation of longer CNTs with average diameter of 40-50 nm.

Design Optimization of Thin-Film Transistors Based on a Metal-Substrate-Semiconductor Architecture for High DC Voltage Sensing

We discuss the potential application of high dc voltage sensing using thin-film transistors (TFTs) on flexible substrates. High voltage sensing has potential applications for power transmission instrumentation. For this, we consider a gate metal-substrate-semiconductor architecture for TFTs. In this architecture, the flexible substrate not only provides mechanical support but also plays the role of the gate dielectric of the TFT. Hence, the thickness of the substrate needs to be optimized for maximizing transconductance, minimizing mechanical stress, and minimizing gate leakage currents. We discuss this optimization, and develop n-type and p-type organic TFTs using polyvinyldene fluoride as the substrate-gate insulator. Circuits are also realized to achieve level shifting, amplification, and high drain voltage operation.

SMO: An Integrated Approach to Intra-array and Inter-array Storage Optimization

The polyhedral model provides an expressive intermediate representation that is convenient for the analysis and subsequent transformation of affine loop nests. Several heuristics exist for achieving complex program transformations in this model. However, there is also considerable scope to utilize this model to tackle the problem of automatic memory footprint optimization. In this paper, we present a new automatic storage optimization technique which can be used to achieve both intra-array as well as inter-array storage reuse with a pre-determined schedule for the computation. Our approach works by finding statement-wise storage partitioning hyper planes that partition a unified global array space so that values with overlapping live ranges are not mapped to the same partition. Our heuristic is driven by a fourfold objective function which not only minimizes the dimensionality and storage requirements of arrays required for each high-level statement, but also maximizes inter statement storage reuse. The storage mappings obtained using our heuristic can be asymptotically better than those obtained by any existing technique. We implement our technique and demonstrate its practical impact by evaluating its effectiveness on several benchmarks chosen from the domains of image processing, stencil computations, and high-performance computing.