Optimization of bus allocation to depots by minimizing dead kilometers

In metropolitan cities, public transportation service plays a vital role in mobility of people, and it has to introduce new routes more frequently due to the fast development of the city in terms of population growth and city size. Whenever there is introduction of new route or increase in frequency of buses, the nonrevenue kilometers covered by the buses increases as depot and route starting/ending points are at different places. This non-revenue kilometers or dead kilometers depends on the distance between depot and route starting point/ending point. The dead kilometers not only results in revenue loss but also results in an increase in the operating cost because of the extra kilometers covered by buses. Reduction of dead kilometers is necessary for the economic growth of the public transportation system. Therefore, in this study, the attention is focused on minimizing dead kilometers by optimizing allocation of buses to depots depending upon the shortest distance between depot and route starting/ending points. We consider also depot capacity and time period of operation during allocation of buses to ensure parking safety and proper maintenance of buses. Mathematical model is developed considering the aforementioned parameters, which is a mixed integer program, and applied to Bangalore Metropolitan Transport Corporation (BMTC) routes operating presently in order to obtain optimal bus allocation to depots. Database for dead kilometers of depots in BMTC for all the schedules are generated using the Form-4 (trip sheet) of each schedule to analyze depot-wise and division-wise dead kilometers. This study also suggests alternative locations where depots can be located to reduce dead kilometers. Copyright (C) 2015 John Wiley & Sons, Ltd.

PolyMage: Automatic Optimization for Image Processing Pipelines

This paper presents the design and implementation of PolyMage, a domain-specific language and compiler for image processing pipelines. An image processing pipeline can be viewed as a graph of interconnected stages which process images successively. Each stage typically performs one of point-wise, stencil, reduction or data-dependent operations on image pixels. Individual stages in a pipeline typically exhibit abundant data parallelism that can be exploited with relative ease. However, the stages also require high memory bandwidth preventing effective utilization of parallelism available on modern architectures. For applications that demand high performance, the traditional options are to use optimized libraries like OpenCV or to optimize manually. While using libraries precludes optimization across library routines, manual optimization accounting for both parallelism and locality is very tedious. The focus of our system, PolyMage, is on automatically generating high-performance implementations of image processing pipelines expressed in a high-level declarative language. Our optimization approach primarily relies on the transformation and code generation capabilities of the polyhedral compiler framework. To the best of our knowledge, this is the first model-driven compiler for image processing pipelines that performs complex fusion, tiling, and storage optimization automatically. Experimental results on a modern multicore system show that the performance achieved by our automatic approach is up to 1.81x better than that achieved through manual tuning in Halide, a state-of-the-art language and compiler for image processing pipelines. For a camera raw image processing pipeline, our performance is comparable to that of a hand-tuned implementation.

Conversion of plastic waste into CNTs using Ni/Mo/MgO catalystAn optimization approach by mixture experiment

A combustion technique is used to study the synthesis of carbon nano tubes from waste plastic as a precursor and Ni/Mo/MgO as a catalyst. The catalytic activity of three components Ni, Mo, MgO is measured in terms of amount of carbon product obtained. Different proportions of metal ions are optimized using mixture experiment in Design expert software. D-optimal design technique is adopted due to nonsimplex region and presence of constraints in the mixture experiment. The activity of the components is observed to be interdependent and the component Ni is found to be more effective. The catalyst containing Ni0.8Mo0.1MgO0.1 yields more carbon product. The structure of catalyst and CNTs are studied by using SEM, XRD, and Raman spectroscopy. SEM analysis shows the formation of longer CNTs with average diameter of 40-50 nm.

Design Optimization of Thin-Film Transistors Based on a Metal-Substrate-Semiconductor Architecture for High DC Voltage Sensing

We discuss the potential application of high dc voltage sensing using thin-film transistors (TFTs) on flexible substrates. High voltage sensing has potential applications for power transmission instrumentation. For this, we consider a gate metal-substrate-semiconductor architecture for TFTs. In this architecture, the flexible substrate not only provides mechanical support but also plays the role of the gate dielectric of the TFT. Hence, the thickness of the substrate needs to be optimized for maximizing transconductance, minimizing mechanical stress, and minimizing gate leakage currents. We discuss this optimization, and develop n-type and p-type organic TFTs using polyvinyldene fluoride as the substrate-gate insulator. Circuits are also realized to achieve level shifting, amplification, and high drain voltage operation.

SMO: An Integrated Approach to Intra-array and Inter-array Storage Optimization

The polyhedral model provides an expressive intermediate representation that is convenient for the analysis and subsequent transformation of affine loop nests. Several heuristics exist for achieving complex program transformations in this model. However, there is also considerable scope to utilize this model to tackle the problem of automatic memory footprint optimization. In this paper, we present a new automatic storage optimization technique which can be used to achieve both intra-array as well as inter-array storage reuse with a pre-determined schedule for the computation. Our approach works by finding statement-wise storage partitioning hyper planes that partition a unified global array space so that values with overlapping live ranges are not mapped to the same partition. Our heuristic is driven by a fourfold objective function which not only minimizes the dimensionality and storage requirements of arrays required for each high-level statement, but also maximizes inter statement storage reuse. The storage mappings obtained using our heuristic can be asymptotically better than those obtained by any existing technique. We implement our technique and demonstrate its practical impact by evaluating its effectiveness on several benchmarks chosen from the domains of image processing, stencil computations, and high-performance computing.