Adaptive Pulse Width Control and Sampling for Low Power Pulse Oximetry

Remote sensing of physiological parameters could be a cost effective approach to improving health care, and low-power sensors are essential for remote sensing because these sensors are often energy constrained. This paper presents a power optimized photoplethysmographic sensor interface to sense arterial oxygen saturation, a technique to dynamically trade off SNR for power during sensor operation, and a simple algorithm to choose when to acquire samples in photoplethysmography. A prototype of the proposed pulse oximeter built using commercial-off-the-shelf (COTS) components is tested on 10 adults. The dynamic adaptation techniques described reduce power consumption considerably compared to our reference implementation, and our approach is competitive to state-of-the-art implementations. The techniques presented in this paper may be applied to low-power sensor interface designs where acquiring samples is expensive in terms of power as epitomized by pulse oximetry.

A 0.5-2.0 GHz injection locked oscillator cascade for parallel wideband RF spectrum sensing

An area-efficient, wideband RF frequency synthesizer, which simultaneously generates multiple local oscillator (LO) signals, is designed. It is suitable for parallel wideband RF spectrum sensing in cognitive radios. The frequency synthesizer consists of an injection locked oscillator cascade (ILOC) where all the LO signals are derived from a single reference oscillator. The ILOC is implemented in a 130-nm technology with an active area of . It generates 4 uniformly spaced LO carrier frequencies from 500 MHz to 2 GHz. This design is the first known implementation of a CMOS based ILOC for wide-band RF spectrum sensing applications.

Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat

The growing number of applications and processing units in modern Multiprocessor Systems-on-Chips (MPSoCs) come along with reduced time to market. Different IP cores can come from different vendors, and their trust levels are also different, but typically they use Network-on-Chip (NoC) as their communication infrastructure. An MPSoC can have multiple Trusted Execution Environments (TEEs). Apart from performance, power, and area research in the field of MPSoC, robust and secure system design is also gaining importance in the research community. To build a secure system, the designer must know beforehand all kinds of attack possibilities for the respective system (MPSoC). In this paper we survey the possible attack scenarios on present-day MPSoCs and investigate a new attack scenario, i.e., router attack targeted toward NoC architecture. We show the validity of this attack by analyzing different present-day NoC architectures and show that they are all vulnerable to this type of attack. By launching a router attack, an attacker can control the whole chip very easily, which makes it a very serious issue. Both routing tables and routing logic-based routers are vulnerable to such attacks. In this paper, we address attacks on routing tables. We propose different monitoring-based countermeasures against routing table-based router attack in an MPSoC having multiple TEEs. Synthesis results show that proposed countermeasures, viz. Runtime-monitor, Restart-monitor, Intermediate manager, and Auditor, occupy areas that are 26.6, 22, 0.2, and 12.2 % of a routing table-based router area. Apart from these, we propose Ejection address checker and Local monitoring module inside a router that cause 3.4 and 10.6 % increase of a router area, respectively. Simulation results are also given, which shows effectiveness of proposed monitoring-based countermeasures.

The two-component signalling networks of Mycobacterium tuberculosis display extensive cross-talk in vitro

Two-component systems (TCSs), which contain paired sensor kinase and response regulator proteins, form the primary apparatus for sensing and responding to environmental cues in bacteria. TCSs are thought to be highly specific, displaying minimal cross-talk, primarily due to the co-evolution of the participating proteins. To assess the level of cross-talk between the TCSs of Mycobacterium tuberculosis, we mapped the complete interactome of the M. tuberculosis TCSs using phosphotransfer profiling. Surprisingly, we found extensive crosstalk among the M. tuberculosis TCSs, significantly more than that in the TCSs in Escherichia coli or Caulobacter crescentus, thereby offering an alternate to specificity paradigm in TCS signalling. Nearly half of the interactions we detected were significant novel cross-interactions, unravelling a potentially complex signalling landscape. We classified the TCSs into specific `one-to-one' and promiscuous `one-to-many' and `many-to-one' circuits. Using mathematical modelling, we deduced that the promiscuous signalling observed can explain several currently confounding observations about M. tuberculosis TCSs. Our findings suggest an alternative paradigm of bacterial signalling with significant cross-talk between TCSs yielding potentially complex signalling landscapes.

Load Balancing with Availability Checker and Load Reporters (LB-ACLRs) for improved Performance in Distributed Systems

Distributed system has quite a lot of servers to attain increased availability of service and for fault tolerance. Balancing the load among these servers is an important task to achieve better performance. There are various hardware and software based load balancing solutions available. However there is always an overhead on Servers and the Load Balancer while communicating with each other and sharing their availability and the current load status information. Load balancer is always busy in listening to clients' request and redirecting them. It also needs to collect the servers' availability status frequently, to keep itself up-to-date. Servers are busy in not only providing service to clients but also sharing their current load information with load balancing algorithms. In this paper we have proposed and discussed the concept and system model for software based load balancer along with Availability-Checker and Load Reporters (LB-ACLRs) which reduces the overhead on server and the load balancer. We have also described the architectural components with their roles and responsibilities. We have presented a detailed analysis to show how our proposed Availability Checker significantly increases the performance of the system.

Part II: Design of Well Doping Profile for Improved Breakdown and Mixed-Signal Performance of STI-Type DePMOS Device

Shallow-trench isolation drain extended pMOS (STI-DePMOS) devices show a distinct two-stage breakdown. The impact of p-well and deep-n-well doping profile on breakdown characteristics is investigated based on TCAD simulations. Design guidelines for p-well and deep-n-well doping profile are developed to shift the onset of the first-stage breakdown to a higher drain voltage and to avoid vertical punch-through leading to early breakdown. An optimal ratio between the OFF-state breakdown voltage and the ON-state resistance could be obtained. Furthermore, the impact of p-well/deep-n-well doping profile on the figure of merits of analog and digital performance is studied. This paper aids in the design of STI drain extended MOSFET devices for widest safe operating area and optimal mixed-signal performance in advanced system-on-chip input-output process technologies.

A Mitigation Technique for Harmonic Downconversion in Wideband Spectrum Sensors

The down conversion of radio frequency components around the harmonics of the local oscillator (LO), and its impact on the accuracy of white space detection using integrated spectrum sensors, is studied. We propose an algorithm to mitigate the impact of harmonic downconversion by utilizing multiple parallel downconverters in the system architecture. The proposed algorithm is validated on a test-board using commercially available integrated circuits and a test-chip implemented in a 130-nm CMOS technology. The measured data show that the impact of the harmonic downconversion is closely related to the LO characteristics, and that much of it can be mitigated by the proposed technique.

On the Equivalence of Acoustic Impedance and Squeeze Film Impedance in Micromechanical Resonators

In this work, we address the issue of modeling squeeze film damping in nontrivial geometries that are not amenable to analytical solutions. The design and analysis of microelectromechanical systems (MEMS) resonators, especially those that use platelike two-dimensional structures, require structural dynamic response over the entire range of frequencies of interest. This response calculation typically involves the analysis of squeeze film effects and acoustic radiation losses. The acoustic analysis of vibrating plates is a very well understood problem that is routinely carried out using the equivalent electrical circuits that employ lumped parameters (LP) for acoustic impedance. Here, we present a method to use the same circuit with the same elements to account for the squeeze film effects as well by establishing an equivalence between the parameters of the two domains through a rescaled equivalent relationship between the acoustic impedance and the squeeze film impedance. Our analysis is based on a simple observation that the squeeze film impedance rescaled by a factor of jx, where x is the frequency of oscillation, qualitatively mimics the acoustic impedance over a large frequency range. We present a method to curvefit the numerically simulated stiffness and damping coefficients which are obtained using finite element analysis (FEA) analysis. A significant advantage of the proposed method is that it is applicable to any trivial/nontrivial geometry. It requires very limited finite element method (FEM) runs within the frequency range of interest, hence reducing the computational cost, yet modeling the behavior in the entire range accurately. We demonstrate the method using one trivial and one nontrivial geometry.

An efficient design of serial and parallel memory using Quantum dot cellular automata

Quantum cellular automata (QCA) is a new technology in the nanometer scale and has been considered as one of the alternative to CMOS technology. In this paper, we describe the design and layout of a serial memory and parallel memory, showing the layout of individual memory cells. Assuming that we can fabricate cells which are separated by 10nm, memory capacities of over 1.6 Gbit/cm2 can be achieved. Simulations on the proposed memories were carried out using QCADesigner, a layout and simulation tool for QCA. During the design, we have tried to reduce the number of cells as well as to reduce the area which is found to be 86.16sq mm and 0.12 nm2 area with the QCA based memory cell. We have also achieved an increase in efficiency by 40%.These circuits are the building block of nano processors and provide us to understand the nano devices of the future.

Design Optimization of Thin-Film Transistors Based on a Metal-Substrate-Semiconductor Architecture for High DC Voltage Sensing

We discuss the potential application of high dc voltage sensing using thin-film transistors (TFTs) on flexible substrates. High voltage sensing has potential applications for power transmission instrumentation. For this, we consider a gate metal-substrate-semiconductor architecture for TFTs. In this architecture, the flexible substrate not only provides mechanical support but also plays the role of the gate dielectric of the TFT. Hence, the thickness of the substrate needs to be optimized for maximizing transconductance, minimizing mechanical stress, and minimizing gate leakage currents. We discuss this optimization, and develop n-type and p-type organic TFTs using polyvinyldene fluoride as the substrate-gate insulator. Circuits are also realized to achieve level shifting, amplification, and high drain voltage operation.