Reducing Buffer Requirements in Core Routers using Dynamic Buffering

Earlier studies have exploited statistical multiplexing of flows in the core of the Internet to reduce the buffer requirement in routers. Reducing the memory requirement of routers is important as it enables an improvement in performance and at the same time a decrease in the cost. In this paper, we observe that the links in the core of the Internet are typically over-provisioned and this can be exploited to reduce the buffering requirement in routers. The small on-chip memory of a network processor (NP) can be effectively used to buffer packets during most regimes of traffic. We propose a dynamic buffering strategy which buffers packets in the receive and transmit buffers of a NP when the memory requirement is low. When the buffer requirement increases due to bursts in the traffic, memory is allocated to packets in the off-chip DRAM. This scheme effectively mitigates the DRAM access bottleneck, as only a part of the traffic is stored in the DRAM. We build a Petri net model and evaluate the proposed scheme with core Internet like traffic. At 77% link utilization, the dynamic buffering scheme has a drop rate of just 0.65%, whereas the traditional DRAM buffering has 4.64% packet drop rate. Even with a high link utilization of 90%, which rarely happens in the core, our dynamic buffering results in a packet drop rate of only 2.17%, while supporting a throughput of 7.39 Gbps. We study the proposed scheme under different conditions to understand the provisioning of processing threads and to determine the queue length at which packets must be buffered in the DRAM. We show that the proposed dynamic buffering strategy drastically reduces the buffering requirement while still maintaining low packet drop rates.

Dynamic contact angle beating from drops impacting onto solid surfaces exhibiting anisotropic wetting

This paper reports an experimental investigation of low Weber number water drops impacting onto solid surfaces exhibiting anisotropic wetting. The wetting anisotropy is created by patterning the solid surfaces with unidirectional parallel grooves. Temporal measurements of impacting drop parameters such as drop base contact diameter, apparent contact angle of drop, and drop height at the center are obtained from high-speed video recordings of drop impacts. The study shows that the impact of low Weber number water drops on the grooved surface exhibits beating phenomenon in the temporal variations of the dynamic contact angle anisotropy and drop height at the center of the impacting drop. It is observed that the beating phenomenon of impacting drop parameters is caused by the frequency difference between the dynamic contact angle oscillations of impacting drop liquid oriented perpendicular and parallel to the direction of grooves on the grooved surface. The primary trigger for the phenomenon is the existence of non-axisymmetric drop flow on the grooved surface featuring pinned and free motions of drop liquid in the directions perpendicular and parallel to the grooves, respectively. The beat frequency is almost independent of the impact drop Weber number. Further experimental measurements with solid surfaces of different groove textures show that the grooved surface with larger wetting anisotropy may be expected to show a dominant beating phenomenon. The phenomenon is gradually damped out with time and is fully unrecognizable at higher drop impact Weber numbers. (C) 2011 Elsevier B.V. All rights reserved.

Compiler-Directed Dynamic Voltage Scaling using Program Phases

Energy consumption has become a major constraint in providing increased functionality for devices with small form factors. Dynamic voltage and frequency scaling has been identified as an effective approach for reducing the energy consumption of embedded systems. Earlier works on dynamic voltage scaling focused mainly on performing voltage scaling when the CPU is waiting for memory subsystem or concentrated chiefly on loop nests and/or subroutine calls having sufficient number of dynamic instructions. This paper concentrates on coarser program regions and for the first time uses program phase behavior for performing dynamic voltage scaling. Program phases are annotated at compile time with mode switch instructions. Further, we relate the Dynamic Voltage Scaling Problem to the Multiple Choice Knapsack Problem, and use well known heuristics to solve it efficiently. Also, we develop a simple integer linear program formulation for this problem. Experimental evaluation on a set of media applications reveal that our heuristic method obtains a 38% reduction in energy consumption on an average, with a performance degradation of 1% and upto 45% reduction in energy with a performance degradation of 5%. Further, the energy consumed by the heuristic solution is within 1% of the optimal solution obtained from the ILP approach.