169 resultados para Integrated circuit layout
Resumo:
Cobalt integrated zinc oxide nanorod (Co-ZnO NR) array is presented as a novel heterostructure for ultraviolet (UV) photodetector (PD). Defect states in Co-ZnO NRs surface induces an enhancement in photocurrent as compared to pristine ZnO NRs PD. Presented Co-ZnO NRs PD is highly sensitive to external magnetic field that demonstrated 185.7% enhancement in response current. It is concluded that the opposite polarizations of electron and holes in the presence of external magnetic field contribute to effective separation of electron hole pairs that have drifted upon UV illumination. Moreover, Co-ZnO NRs PD shows a faster photodetection speed (1.2 s response time and 7.4 s recovery time) as compared to the pristine ZnO NRs where the response and recovery times are observed as 38 and 195 s, respectively.
Resumo:
This letter presents an alternate proof for the steady-state equivalent circuit of a doubly fed induction machine operating at supersynchronous speeds. The spatial orientation of rotating magnetic fields is used to validate the conjugation of rotor side quantities arising in supersynchronous mode. The equivalent circuit is further validated using dynamic simulations of a stand-alone machine.
Resumo:
We report on the fabrication of microfluidc-nanofluidic channels on Si incorporated with embedded metallic interconnects. The device aids the study of motion of dispersed particles relative to the fluid under the influence of spatially uniform electric field. Optical lithography in combination with focused ion beam technique was used to fabricate the microfluidic-nanofluidic channels, respectively. Focused ion beam technique was also used for embedding the electrodes in the nanochannel. Gold contact pads were deposited using sputtering. The substrate was finally anodically bonded to a glass substrate.
Resumo:
The polyhedral model provides an expressive intermediate representation that is convenient for the analysis and subsequent transformation of affine loop nests. Several heuristics exist for achieving complex program transformations in this model. However, there is also considerable scope to utilize this model to tackle the problem of automatic memory footprint optimization. In this paper, we present a new automatic storage optimization technique which can be used to achieve both intra-array as well as inter-array storage reuse with a pre-determined schedule for the computation. Our approach works by finding statement-wise storage partitioning hyper planes that partition a unified global array space so that values with overlapping live ranges are not mapped to the same partition. Our heuristic is driven by a fourfold objective function which not only minimizes the dimensionality and storage requirements of arrays required for each high-level statement, but also maximizes inter statement storage reuse. The storage mappings obtained using our heuristic can be asymptotically better than those obtained by any existing technique. We implement our technique and demonstrate its practical impact by evaluating its effectiveness on several benchmarks chosen from the domains of image processing, stencil computations, and high-performance computing.