Threshold voltage model for accumulation mode polycrystalline SOI MOSFETs and comparisons with experimental results

In this paper, a simple but accurate semi analytical charge sheet model is presented for threshold voltage of accumulation mode polycrystalline silicon on insulator (PSOI) MOSFETs. In this model, we define the threshold voltage (V-T) of the polysilicon accumulation mode MOSFET as the gate voltage required to raise the surface potential (phi(s)) to a value phi(sT) necessary to overcome the charge trapping in the grain boundary and to create channel accumulation charge that is equal to the channel accumulation charge available in the case of single crystal silicon accumulation mode MOSFET at that phi(sT). The correctness of the model is demonstrated by comparing the theoretically estimated values of threshold voltage with the experimentally measured threshold voltages on the accumulation mode PSOI MOSFETs fabricated in the laboratory using LPCVD polysilicon layers doped with boron to achieve dopant densities in the range 3.3 x 10(-15)-5 x 10(17)/cm(3). Further, it is shown that the threshold voltage values of accumulation mode PSOI MOSFETs predicted by the present model match very closely with the experimental results, better than those obtained with the models previously reported in the literature. (C) 2012 Elsevier B.V. All rights reserved.

Graphene transistors for CMOS applications: opportunities and challenges

In the last decade, there has been a tremendous interest in Graphene transistors. The greatest advantage for CMOS nanoelectronics applications is the fact that Graphene is compatible with planar CMOS technology and potentially offers excellent short channel properties. Because of the zero bandgap, it will not be possible to turn off the MOSFET efficiently and hence the typical on current to off current ratio (Ion/Ioff) has been less than 10. Several techniques have been proposed to open the bandgap in Graphene. It has been demonstrated, both theoretically and experimentally, that Graphene Nanoribbons (GNR) show a bandgap which is inversely proportional to their width. GNRs with about 20 nm width have bandgaps in the range of 100meV. But it is very difficult to obtain GNRs with well defined edges. An alternate technique to open the band gap is to use bilayer Graphene (BLG), with an asymmetric bias applied in the direction perpendicular to their plane. Another important CMOS metric, the subthreshold slope is also limited by the inability to turn off the transistor. However, these devices could be attractive for RF CMOS applications. But even for analog and RF applications the non-saturating behavior of the drain current can be an issue. Although some studies have reported current saturation, the mechanisms are still not very clear. In this talk we present some of our recent findings, based on simulations and experiments, and propose possible solutions to obtain high on current to off current ratio. A detailed study on high field transport in grapheme transistors, relevant for analog and RF applications will also be presented.

Device oriented statistical modeling method for process variability in 45nm analog CMOS technology

With the rapid scaling down of the semiconductor process technology, the process variation aware circuit design has become essential today. Several statistical models have been proposed to deal with the process variation. We propose an accurate BSIM model for handling variability in 45nm CMOS technology. The MOSFET is designed to meet the specification of low standby power technology of International Technology Roadmap for Semiconductors (ITRS).The process parameters variation of annealing temperature, oxide thickness, halo dose and title angle of halo implant are considered for the model development. One parameter variation at a time is considered for developing the model. The model validation is done by performance matching with device simulation results and reported error is less than 10%.© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

Decoherence suppression by parallelization

Decoherence as an obstacle in quantum computation is viewed as a struggle between two forces [1]: the computation which uses the exponential dimension of Hilbert space, and decoherence which destroys this entanglement by collapse. In this model of decohered quantum computation, a sequential quantum computer loses the battle, because at each time step, only a local operation is carried out but g*(t) number of gates collapse. With quantum circuits computing in parallel way the situation is different- g(t) number of gates can be applied at each time step and number gates collapse because of decoherence. As g(t) ≈ g*(t) competition here is even [1]. Our paper improves on this model by slowing down g*(t) by encoding the circuit in parallel computing architectures and running it in Single Instruction Multiple Data (SIMD) paradigm. We have proposed a parallel ion trap architecture for single-bit rotation of a qubit.

Low complexity adaptation for channel shortening equalizers

Since the days of Digital Subscriber Links(DSL), Time Domain Equalizers(TEQ's) have been used to combat time dispersive channels in Multicarrier Systems. In this paper, we propose computationally inexpensive techniques to recompute TEQ weights in the presence of changes in the channel, especially over fast fading channels. The techniques use no extra information except the perturbation itself, and provide excellent approximations to the new TEQ weights. The proposed adaptation techniques are shown to perform admirably well for small changes in channels for OFDM systems.

Comparison of one cycle control of charge and current for bi-directional boost rectifiers

Classical control and one cycle control of current are popular methods used to modulate pulses in active rectifiers for ac-dc power conversion. One cycle control has lower control complexity and can be implemented using linear analog circuits when compared with the classical approach. However, it also suffers from problems such as instability and offsets in current that is severe at light load conditions. A control strategy for bidirectional boost rectifiers based on one cycle control of charge is proposed for that overcomes these limitations. The integral of sensed current, which represents charge, is compared with a non-linear carrier, which is modified for ac-dc power conversion. This generates the gating signals for the switching devices. The modifications required for the control law governing one cycle control of charge is derived in the paper. Detailed simulation studies are carried out to compare one cycle control of current with the proposed method for ac-dc power conversion, which are validated on a laboratory hardware prototype.

Performance limits of transition metal dichalcogenide (MX2) nanotube surround gate ballistic field effect transistors

We theoretically analyze the performance of transition metal dichalcogenide (MX2) single wall nanotube (SWNT) surround gate MOSFET, in the 10 nm technology node. We consider semiconducting armchair (n, n) SWNT of MoS2, MoSe2, WS2, and WSe2 for our study. The material properties of the nanotubes are evaluated from the density functional theory, and the ballistic device characteristics are obtained by self-consistently solving the Poisson-Schrodinger equation under the non-equilibrium Green's function formalism. Simulated ON currents are in the range of 61-76 mu A for 4.5 nm diameter MX2 tubes, with peak transconductance similar to 175-218 mu S and ON/OFF ratio similar to 0.6 x 10(5)-0.8 x 10(5). The subthreshold slope is similar to 62.22 mV/decade and a nominal drain induced barrier lowering of similar to 12-15 mV/V is observed for the devices. The tungsten dichalcogenide nanotubes offer superior device output characteristics compared to the molybdenum dichalcogenide nanotubes, with WSe2 showing the best performance. Studying SWNT diameters of 2.5-5 nm, it is found that increase in diameter provides smaller carrier effective mass and 4%-6% higher ON currents. Using mean free path calculation to project the quasi-ballistic currents, 62%-75% reduction from ballistic values in drain current in long channel lengths of 100, 200 nm is observed.

A tuned rectifier for RF energy harvesting from ambient radiations

A circuit topology based on accumulate-and-use philosophy has been developed to harvest RF energy from ambient radiations such as those from cellular towers. Main functional units of this system are antenna, tuned rectifier, supercapacitor, a gated boost converter and the necessary power management circuits. Various RF aspects of the design philosophy for maximizing the conversion efficiency at an input power level of 15 mu W are presented here. The system is characterized in an anechoic chamber and it has been established that this topology can harvest RF power densities as low as 180 mu W/m(2) and can adaptively operate the load depending on the incident radiation levels. The output of this system can be easily configured at a desired voltage in the range 2.2-4.5 V. A practical CMOS load - a low power wireless radio module has been demonstrated to operate intermittently by this approach. This topology can be easily modified for driving other practical loads, from harvested RF energy at different frequencies and power levels.

Information and Efficiency in the Nervous System-A Synthesis

In systems biology, questions concerning the molecular and cellular makeup of an organism are of utmost importance, especially when trying to understand how unreliable components-like genetic circuits, biochemical cascades, and ion channels, among others-enable reliable and adaptive behaviour. The repertoire and speed of biological computations are limited by thermodynamic or metabolic constraints: an example can be found in neurons, where fluctuations in biophysical states limit the information they can encode-with almost 20-60% of the total energy allocated for the brain used for signalling purposes, either via action potentials or by synaptic transmission. Here, we consider the imperatives for neurons to optimise computational and metabolic efficiency, wherein benefits and costs trade-off against each other in the context of self-organised and adaptive behaviour. In particular, we try to link information theoretic (variational) and thermodynamic (Helmholtz) free-energy formulations of neuronal processing and show how they are related in a fundamental way through a complexity minimisation lemma.

Asynchronous Measurement of Transient Phase-Shift Resulting From RF Receiver State-Change

In a wireless receiver, a down-converted RF signal undergoes a transient phase shift, when the gain state is changed to adjust for varying conditions in transmission and propagation. A method is developed, in which such phase shifts are detected asynchronously, and their undesirable effects on the bit error rate are corrected. The method was developed for and used in, the system-level characterization and calibration of a 65-nm CMOS UHF receiver. The phase-shifts associated with specific gain-state transitions were measured within a test framework, and used in the baseband signal processing blocks to compensate for errors, whenever the receiver anticipated a gain-state transition.

Signal Detection in Generalized Gaussian Noise by Nonlinear Wavelet Denoising

In this paper, a nonlinear suboptimal detector whose performance in heavy-tailed noise is significantly better than that of the matched filter is proposed. The detector consists of a nonlinear wavelet denoising filter to enhance the signal-to-noise ratio, followed by a replica correlator. Performance of the detector is investigated through an asymptotic theoretical analysis as well as Monte Carlo simulations. The proposed detector offers the following advantages over the optimal (in the Neyman-Pearson sense) detector: it is easier to implement, and it is more robust with respect to error in modeling the probability distribution of noise.

A power-scalable RF CMOS receiver for 2.4 GHz Wireless Sensor Network applications

A power scalable receiver architecture is presented for low data rate Wireless Sensor Network (WSN) applications in 130nm RF-CMOS technology. Power scalable receiver is motivated by the ability to leverage lower run-time performance requirement to save power. The proposed receiver is able to switch power settings based on available signal and interference levels while maintaining requisite BER. The Low-IF receiver consists of Variable Noise and Linearity LNA, IQ Mixers, VGA, Variable Order Complex Bandpass Filter and Variable Gain and Bandwidth Amplifier (VGBWA) capable of driving variable sampling rate ADC. Various blocks have independent power scaling controls depending on their noise, gain and interference rejection (IR) requirements. The receiver is designed for constant envelope QPSK-type modulation with 2.4GHz RF input, 3MHz IF and 2MHz bandwidth. The chip operates at 1V Vdd with current scalable from 4.5mA to 1.3mA and chip area of 0.65mm2.

Comparison of OpAmp based and comparator based switched capacitor filter

Comparator based switched capacitor circuits provide an excellent opportunity to design sampled data systems where the virtual ground condition is detected rather than being continuously forced with negative feedback in Opamp based circuits. This work is an application of this concept to design a 1 st order 330 KHz cutoff frequency Lowpass filter operating at 10 MHz sampling frequency in 0.13μm technology and 1.2 V supply voltage. The Comparator Based Switched Capacitor (CBSC) filter is compared with conventional Two stage Miller compensated Operational amplifier based switched capacitor filter. It is shown that CBSC filter relaxes the constraints like speed ,linearity, gain, stability which would otherwise be hard to satisfy in scaled technologies in Opamp based circuits. The designed CBSC based lowpass filter provides significant power savings compared to traditional Opamp based switched capacitor filter.

Design Of Start-up Power Circuit For Control Power Supplies With Wide Input Voltage Variation

This paper presents the design of a start up power circuit for a control power supply (CPS) which feeds power to the sub-systems of High Power Converters (HPC). The sub-systems such as gate drive card, annunciation card, protection and delay card etc; needs to be provided power for the operation of a HPC. The control power supply (CPS) is designed to operate over a wide range of input voltage from 90Vac to 270Vac. The CPS output supplies power at a desired voltage of Vout =24V to the auxiliary sub-systems of the HPC. During the starting, the power supply to the control circuitry of CPS in turn, is obtained using a separate start-up power supply. This paper discusses the various design issues of the start-up power circuit to ensure that start-up and shut down of the CPS occurs reliably. The CPS also maintains the power factor close to unity and low total harmonic distortion in input current. The paper also provides design details of gate drive circuits employed for the CPS as well as the design of on-board power supply for the CPS. Index terms: control power supply, start-up power supply, DSFC, pre-regulator

Functional analysis of ultra high information rates conveyed by rat vibrissal primary afferents

Sensory receptors determine the type and the quantity of information available for perception. Here, we quantified and characterized the information transferred by primary afferents in the rat whisker system using neural system identification. Quantification of ``how much'' information is conveyed by primary afferents, using the direct method (DM), a classical information theoretic tool, revealed that primary afferents transfer huge amounts of information (up to 529 bits/s). Information theoretic analysis of instantaneous spike-triggered kinematic stimulus features was used to gain functional insight on ``what'' is coded by primary afferents. Amongst the kinematic variables tested-position, velocity, and acceleration-primary afferent spikes encoded velocity best. The other two variables contributed to information transfer, but only if combined with velocity. We further revealed three additional characteristics that play a role in information transfer by primary afferents. Firstly, primary afferent spikes show preference for well separated multiple stimuli (i.e., well separated sets of combinations of the three instantaneous kinematic variables). Secondly, neurons are sensitive to short strips of the stimulus trajectory (up to 10 ms pre-spike time), and thirdly, they show spike patterns (precise doublet and triplet spiking). In order to deal with these complexities, we used a flexible probabilistic neuron model fitting mixtures of Gaussians to the spike triggered stimulus distributions, which quantitatively captured the contribution of the mentioned features and allowed us to achieve a full functional analysis of the total information rate indicated by the DM. We found that instantaneous position, velocity, and acceleration explained about 50% of the total information rate. Adding a 10 ms pre-spike interval of stimulus trajectory achieved 80-90%. The final 10-20% were found to be due to non-linear coding by spike bursts.