A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs

The charge-pump (CP) mismatch current is a dominant source of static phase error and reference spur in the nano-meter CMOS PLL implementations due to its worsened channel length modulation effect. This paper presents a charge-pump (CP) mismatch current reduction technique utilizing an adaptive body bias tuning of CP transistors and a zero CP mismatch current tracking PLL architecture for reference spur suppression. A chip prototype of the proposed circuit was implemented in 0.13 mu m CMOS technology. The frequency synthesizer consumes 8.2 mA current from a 13 V supply voltage and achieves a phase noise of -96.01 dBc/Hz @ 1 MHz offset from a 2.4 GHz RF carrier. The charge-pump measurements using the proposed calibration technique exhibited a mismatch current of less than 0.3 mu A (0.55%) over the VCO control voltage range of 0.3-1.0 V. The closed loop measurements show a minimized static phase error of within +/- 70 ps and a similar or equal to 9 dB reduction in reference spur level across the PLL output frequency range 2.4-2.5 GHz. The presented CP calibration technique compensates for the DC current mismatch and the mismatch due to channel length modulation effect and therefore improves the performance of CP-PLLs in nano-meter CMOS implementations. (C) 2015 Elsevier Ltd. All rights reserved.

Suspended core-shell Pt-PtOx nanostructure for ultrasensitive hydrogen gas sensor

High sensitivity gas sensors are typically realized using metal catalysts and nanostructured materials, utilizing non-conventional synthesis and processing techniques, incompatible with on-chip integration of sensor arrays. In this work, we report a new device architecture, suspended core-shell Pt-PtOx nanostructure that is fully CMOS-compatible. The device consists of a metal gate core, embedded within a partially suspended semiconductor shell with source and drain contacts in the anchored region. The reduced work function in suspended region, coupled with builtin electric field of metal-semiconductor junction, enables the modulation of drain current, due to room temperature Redox reactions on exposure to gas. The device architecture is validated using Pt-PtO2 suspended nanostructure for sensing H-2 down to 200 ppb under room temperature. By exploiting catalytic activity of PtO2, in conjunction with its p-type semiconducting behavior, we demonstrate about two orders of magnitude improvement in sensitivity and limit of detection, compared to the sensors reported in recent literature. Pt thin film, deposited on SiO2, is lithographically patterned and converted into suspended Pt-PtO2 sensor, in a single step isotropic SiO2 etching. An optimum design space for the sensor is elucidated with the initial Pt film thickness ranging between 10 nm and 30 nm, for low power (< 5 mu W), room temperature operation. (C) 2015 AIP Publishing LLC.

Effect of Chalcogens on Electronic and Photophysical Properties of Vinylene-Based Diketopyrrolopyrrole Copolymers

Three vinylene linked diketopyrrolopyrrole based donor acceptor (D-A) copolymers have been synthesized with phenyl, thienyl, and selenyl units as donors. Optical and electronic properties were investigated with UV-vis absorption spectroscopy, cyclic voltammetry, near edge X-ray absorption spectroscopy, organic field effect transistor (OFET) measurements, and density functional theory (DFT) calculations. Optical and electrochemical band gaps decrease in the order phenyl, thienyl, and selenyl. Only phenyl-based polymers are nonplanar, but the main contributor to the larger band gap is electronic, not structural effects. Thienyl and selenyl polymers exhibit ambipolar charge transport but with higher hole than electron mobility. Experimental and theoretical results predict the selenyl system to have the best transport properties, but OFET measurements prove the thienyl system to be superior with p-channel mobility as high as 0.1 cm(2) V-1 s(-1).

High-Performance Sensors Based on Resistance Fluctuations of Single-Layer-Graphene Transistors

One of the most interesting predicted applications of graphenemonolayer-based devices is as high-quality sensors. In this article, we show, through systematic experiments, a chemical vapor sensor based on the measurement of lowfrequency resistance fluctuations of single-layer-graphene field-effect-transistor devices. The sensor has extremely high sensitivity, very high specificity, high fidelity, and fast response times. The performance of the device using this scheme of measurement (which uses resistance fluctuations as the detection parameter) is more than 2 orders of magnitude better than a detection scheme in which changes in the average value of the resistance is monitored. We propose a number-densityfluctuation-based model to explain the superior characteristics of a noisemeasurement-based detection scheme presented in this article.

Non-enzymatic electronic detection of glucose using aminophenylboronic acid functionalized reduced graphene oxide

We report the non-enzymatic electronic detection of glucose using field effect transistor (FET) devices made of aminophenylboronic acid (APBA) functionalized reduced graphene oxide (RGO). Detection of glucose molecules was carried out over a wide dynamic range of concentration varying from 100 pM to 100 mM with a detection limit of similar to 2 nM using both covalently and non-covalently functionalized APBA-RGO complex. The normalized change in electrical conductance data shows that the FET devices made of non-covalently functionalized APBA-RGO complex (nc-APBA-RGO) exhibited a linear response to glucose aqueous solution of concentrations varying from 1 nM to 10 mM and showed 4 times enhanced sensitivity over the devices made of covalently functionalized APBA-RGO complex (c-APBA-RGO). Specificity of APBA-RGO complex to glucose is confirmed from the observation of negligible change in electrical conductance after exposure to 0.1 mM of lactose and other interfering factors. (C) 2015 Elsevier B.V. All rights reserved.

Part I: Physical Insights Into the Two-Stage Breakdown Characteristics of STI-Type Drain-Extended pMOS Device

In this paper, we study breakdown characteristics in shallow-trench isolation (STI)-type drain-extended MOSFETs (DeMOS) fabricated using a low-power 65-nm triple-well CMOS process with a thin gate oxide. Experimental data of p-type STI-DeMOS device showed distinct two-stage behavior in breakdown characteristics in both OFF-and ON-states, unlike the n-type device, causing a reduction in the breakdown voltage and safe operating area. The first-stage breakdown occurs due to punchthrough in the vertical structure formed by p-well, deep n-well, and p-substrate, whereas the second-stage breakdown occurs due to avalanche breakdown of lateral n-well/p-well junction. The breakdown characteristics are also compared with the STI-DeNMOS device structure. Using the experimental results and advanced TCAD simulations, a complete understanding of breakdown mechanisms is provided in this paper for STI-DeMOS devices in advanced CMOS processes.

A Mitigation Technique for Harmonic Downconversion in Wideband Spectrum Sensors

The down conversion of radio frequency components around the harmonics of the local oscillator (LO), and its impact on the accuracy of white space detection using integrated spectrum sensors, is studied. We propose an algorithm to mitigate the impact of harmonic downconversion by utilizing multiple parallel downconverters in the system architecture. The proposed algorithm is validated on a test-board using commercially available integrated circuits and a test-chip implemented in a 130-nm CMOS technology. The measured data show that the impact of the harmonic downconversion is closely related to the LO characteristics, and that much of it can be mitigated by the proposed technique.

DLTS analysis of amphoteric interface defects in high-TiO2 MOS structures prepared by sol-gel spin-coating

High-kappa TiO2 thin films have been fabricated from a facile, combined sol-gel spin - coating technique on p and n type silicon substrate. XRD and Raman studies headed the existence of anatase phase of TiO2 with a small grain size of 18 nm. The refractive index `n' quantified from ellipsometry is 2.41. AFM studies suggest a high quality, pore free films with a fairly small surface roughness of 6 angstrom. The presence of Ti in its tetravalent state is confirmed by XPS analysis. The defect parameters observed at the interface of Si/TiO2 were studied by capacitance - voltage (C - V) and deep level transient spectroscopy (DLTS). The flat - band voltage (V-FB) and the density of slow interface states estimated are -0.9, -0.44 V and 5.24x10(10), 1.03x10(11) cm(-2); for the NMOS and PMOS capacitors, respectively. The activation energies, interface state densities and capture cross -sections measured by DLTS are E-V + 0.30, E-C - 0.21 eV; 8.73x10(11), 6.41x10(11) eV(-1) cm(-2) and 5.8x10(-23), 8.11x10(-23) cm(2) for the NMOS and PMOS structures, respectively. A low value of interface state density in both P-and N-MOS structures makes it a suitable alternate dielectric layer for CMOS applications. And also very low value of capture cross section for both the carriers due to the amphoteric nature of defect indicates that the traps are not aggressive recombination centers and possibly can not contribute to the device operation to a large extent. (C) 2015 Author(s).

Probing 2D black phosphorus by quantum capacitance measurements

Two-dimensional materials and their heterostructures have emerged as a new class of materials, not only for fundamental physics but also for electronic and optoelectronic applications. Black phosphorus (BP) is a relatively new addition to this class of materials. Its strong in-plane anisotropy makes BP a unique material for making conceptually new types of electronic devices. However, the global density of states (DOS) of BP in device geometry has not been measured experimentally. Here, we report the quantum capacitance measurements together with the conductance measurements on an hBN-protected few-layer BP (similar to six layers) in a dual-gated field effect transistor (FET) geometry. The measured DOS from our quantum capacitance is compared with density functional theory (DFT). Our results reveal that the transport gap for quantum capacitance is smaller than that in conductance measurements due to the presence of localized states near the band edge. The presence of localized states is confirmed by the variable range hopping seen in our temperature dependence conductivity. A large asymmetry is observed between the electron and hole side. This asymmetric nature is attributed to the anisotropic band dispersion of BP. Our measurements establish the uniqueness of quantum capacitance in probing the localized states near the band edge, hitherto not seen in conductance measurements.

High-kappa TiO2 Thin Film Prepared by Sol-Gel Spin-Coating Method

High-k TiO2 thin film on p-type silicon substrate was fabricated by a combined sol-gel and spin coating method. Thus deposited titania film had anatase phase with a small grain size of 16 nm and surface roughness of congruent to 0.6 nm. The oxide capacitance (C-ox), flat band capacitance (C-FB), flat band voltage (V-FB), oxide trapped charge (Q(ot)), calculated from the high frequency (1 MHz) C-V curve were 0.47 nF, 0.16 nF, -0.91 V, 4.7x10(-12) C, respectively. As compared to the previous reports, a high dielectric constant of 94 at 1 MHz frequency was observed in the devices investigated here and an equivalent oxide thickness (EOT) was 4.1 nm. Dispersion in accumulation capacitance shows a linear relationship with AC frequencies. Leakage current density was found in acceptable limits (2.1e-5 A/cm(2) for -1 V and 5.7e-7 A/cm(2) for +1 V) for CMOS applications.

High-kappa TiO2 Thin Film Prepared by Sol-Gel Spin-Coating Method

High-k TiO2 thin film on p-type silicon substrate was fabricated by a combined sol-gel and spin coating method. Thus deposited titania film had anatase phase with a small grain size of 16 nm and surface roughness of congruent to 0.6 nm. The oxide capacitance (C-ox), flat band capacitance (C-FB), flat band voltage (V-FB), oxide trapped charge (Q(ot)), calculated from the high frequency (1 MHz) C-V curve were 0.47 nF, 0.16 nF, -0.91 V, 4.7x10(-12) C, respectively. As compared to the previous reports, a high dielectric constant of 94 at 1 MHz frequency was observed in the devices investigated here and an equivalent oxide thickness (EOT) was 4.1 nm. Dispersion in accumulation capacitance shows a linear relationship with AC frequencies. Leakage current density was found in acceptable limits (2.1e-5 A/cm(2) for -1 V and 5.7e-7 A/cm(2) for +1 V) for CMOS applications.

An efficient design of serial and parallel memory using Quantum dot cellular automata

Quantum cellular automata (QCA) is a new technology in the nanometer scale and has been considered as one of the alternative to CMOS technology. In this paper, we describe the design and layout of a serial memory and parallel memory, showing the layout of individual memory cells. Assuming that we can fabricate cells which are separated by 10nm, memory capacities of over 1.6 Gbit/cm2 can be achieved. Simulations on the proposed memories were carried out using QCADesigner, a layout and simulation tool for QCA. During the design, we have tried to reduce the number of cells as well as to reduce the area which is found to be 86.16sq mm and 0.12 nm2 area with the QCA based memory cell. We have also achieved an increase in efficiency by 40%.These circuits are the building block of nano processors and provide us to understand the nano devices of the future.

Electron mobility in few-layer MoxW1-xS2

Heterostructures of two-dimensional (2D) layered materials are increasingly being explored for electronics in order to potentially extend conventional transistor scaling and to exploit new device designs and architectures. Alloys form a key underpinning of any heterostructure device technology and therefore an understanding of their electronic properties is essential. In this paper, we study the intrinsic electron mobility in few-layer MoxW1-xS2 as limited by various scattering mechanisms. The room temperature, energy-dependent scattering times corresponding to polar longitudinal optical (LO) phonon, alloy and background impurity scattering mechanisms are estimated based on the Born approximation to Fermi's golden rule. The contribution of individual scattering rates is analyzed as a function of 2D electron density as well as of alloy composition in MoxW1-xS2. While impurity scattering limits the mobility for low carrier densities (<2-4x10(12) cm(-2)), LO polar phonon scattering is the dominant mechanism for high electron densities. Alloy scattering is found to play a non-negligible role for 0.5 < x < 0.7 in MoxW1-xS2. The LO phonon-limited and impurity-limited mobilities show opposing trends with respect to alloy mole fractions. The understanding of electron mobility in MoxW1-xS2 presented here is expected to enable the design and realization of heterostructures and devices based on alloys of MoS2 andWS(2).

Electron mobility in few-layer MoxW1-xS2

Heterostructures of two-dimensional (2D) layered materials are increasingly being explored for electronics in order to potentially extend conventional transistor scaling and to exploit new device designs and architectures. Alloys form a key underpinning of any heterostructure device technology and therefore an understanding of their electronic properties is essential. In this paper, we study the intrinsic electron mobility in few-layer MoxW1-xS2 as limited by various scattering mechanisms. The room temperature, energy-dependent scattering times corresponding to polar longitudinal optical (LO) phonon, alloy and background impurity scattering mechanisms are estimated based on the Born approximation to Fermi's golden rule. The contribution of individual scattering rates is analyzed as a function of 2D electron density as well as of alloy composition in MoxW1-xS2. While impurity scattering limits the mobility for low carrier densities (<2-4x10(12) cm(-2)), LO polar phonon scattering is the dominant mechanism for high electron densities. Alloy scattering is found to play a non-negligible role for 0.5 < x < 0.7 in MoxW1-xS2. The LO phonon-limited and impurity-limited mobilities show opposing trends with respect to alloy mole fractions. The understanding of electron mobility in MoxW1-xS2 presented here is expected to enable the design and realization of heterostructures and devices based on alloys of MoS2 andWS(2).

Enhancing photoresponsivity using MoTe2-graphene vertical heterostructures

MoTe2 with a narrow band-gap of similar to 1.1 eV is a promising candidate for optoelectronic applications, especially for the near-infrared photo detection. However, the photo responsivity of few layers MoTe2 is very small (<1mAW(-1)). In this work, we show that a few layer MoTe2-graphene vertical heterostructures have a much larger photo responsivity of similar to 20mAW(-1). The trans-conductance measurements with back gate voltage show on-off ratio of the vertical transistor to be similar to(0.5-1) x 10(5). The rectification nature of the source-drain current with the back gate voltage reveals the presence of a stronger Schottky barrier at the MoTe2-metal contact as compared to the MoTe2-graphene interface. In order to quantify the barrier height, it is essential to measure the work function of a few layers MoTe2, not known so far. We demonstrate a method to determine the work function by measuring the photo-response of the vertical transistor as a function of the Schottky barrier height at the MoTe2-graphene interface tuned by electrolytic top gating. (C) 2016 AIP Publishing LLC.