140 resultados para Hardware gràfic


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In this work, spectrum sensing for cognitive radios is considered in the presence of multiple Primary Users (PU) using frequency-hopping communication over a set of frequency bands. The detection performance of the Fast Fourier Transform (FFT) Average Ratio (FAR) algorithm is obtained in closed-form, for a given FFT size and number of PUs. The effective throughput of the Secondary Users (SU) is formulated as an optimization problem with a constraint on the maximum allowable interference on the primary network. Given the hopping period of the PUs, the sensing duration that maximizes the SU throughput is derived. The results are validated using Monte Carlo simulations. Further, an implementation of the FAR algorithm on the Lyrtech (now, Nutaq) small form factor software defined radio development platform is presented, and the performance recorded through the hardware is observed to corroborate well with that obtained through simulations, allowing for implementation losses. (C) 2015 Elsevier B.V. All rights reserved.

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Graph algorithms have been shown to possess enough parallelism to keep several computing resources busy-even hundreds of cores on a GPU. Unfortunately, tuning their implementation for efficient execution on a particular hardware configuration of heterogeneous systems consisting of multicore CPUs and GPUs is challenging, time consuming, and error prone. To address these issues, we propose a domain-specific language (DSL), Falcon, for implementing graph algorithms that (i) abstracts the hardware, (ii) provides constructs to write explicitly parallel programs at a higher level, and (iii) can work with general algorithms that may change the graph structure (morph algorithms). We illustrate the usage of our DSL to implement local computation algorithms (that do not change the graph structure) and morph algorithms such as Delaunay mesh refinement, survey propagation, and dynamic SSSP on GPU and multicore CPUs. Using a set of benchmark graphs, we illustrate that the generated code performs close to the state-of-the-art hand-tuned implementations.

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Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector (SV) structures have advantages like extension of linear modulation range, elimination of fifth and seventh harmonics in phase voltages and currents for the full modulation range including extreme 12-step operation, reduced device voltage ratings, lesser dv/dt stresses on devices and motor phase windings resulting in lower EMI/EMC problems, and lower switching frequency-making it more suitable for high-power drive applications. This paper proposes a simple method to obtain pulsewidth modulation (PWM) timings for a dodecagonal voltage SV structure using only sampled reference voltages. In addition to this, a carrier-based method for obtaining the PWM timings for a general N-level dodecagonal structure is proposed in this paper for the first time. The algorithm outputs the triangle information and the PWM timing values which can be set as the compare values for any carrier-based hardware PWM module to obtain SV PWM like switching sequences. The proposed method eliminates the need for angle estimation, computation of modulation indices, and iterative search algorithms that are typical in multilevel dodecagonal SV systems. The proposed PWM scheme was implemented on a five-level dodecagonal SV structure. Exhaustive simulation and experimental results for steady-state and transient conditions are presented to validate the proposed method.

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In this article, a Field Programmable Gate Array (FPGA)-based hardware accelerator for 3D electromagnetic extraction, using Method of Moments (MoM) is presented. As the number of nets or ports in a system increases, leading to a corresponding increase in the number of right-hand-side (RHS) vectors, the computational cost for multiple matrix-vector products presents a time bottleneck in a linear-complexity fast solver framework. In this work, an FPGA-based hardware implementation is proposed toward a two-level parallelization scheme: (i) matrix level parallelization for single RHS and (ii) pipelining for multiple-RHS. The method is applied to accelerate electrostatic parasitic capacitance extraction of multiple nets in a Ball Grid Array (BGA) package. The acceleration is shown to be linearly scalable with FPGA resources and speed-ups over 10x against equivalent software implementation on a 2.4GHz Intel Core i5 processor is achieved using a Virtex-6 XC6VLX240T FPGA on Xilinx's ML605 board with the implemented design operating at 200MHz clock frequency. (c) 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:776-783, 2016

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Corona discharges resulting from the metal parts of insulators and the line hardware affect the long term performance of the polymeric insulators used for outdoor application and can lead to its eventual failure. The authors previous work, involved in developing a new methodology to evaluate the performance of polymeric shed materials subjected to corona stresses in the presence of natural fog condition, results revealed more surface hydroxylation thereby resulting in more loss of hydropobhicity. With the increase in industrialization, there is an increase in acidic component of the rain as well as the fog (moisture). The present work, reports the effect of acid fog on the corona performance of the polymeric insulators for both AC and DC excitation, interesting results are obtained. A comparison of the experimental investigations revealed that the acidic fog has more effect than that of the normal fog. This fact has been confirmed by physico-chemical analysis like the scanning electron microscopy (SEM), Fourier transform infrared spectroscopy (FTIR), x-ray photoelectron spectroscopy (XPS) and contact angle measurement. The effect of DC corona is found to be lesser in comparison with the AC; however the hydroxylation induced by the DC corona under the presence of fog is similar with that of AC excitation.