Electron mobility in few-layer MoxW1-xS2

Heterostructures of two-dimensional (2D) layered materials are increasingly being explored for electronics in order to potentially extend conventional transistor scaling and to exploit new device designs and architectures. Alloys form a key underpinning of any heterostructure device technology and therefore an understanding of their electronic properties is essential. In this paper, we study the intrinsic electron mobility in few-layer MoxW1-xS2 as limited by various scattering mechanisms. The room temperature, energy-dependent scattering times corresponding to polar longitudinal optical (LO) phonon, alloy and background impurity scattering mechanisms are estimated based on the Born approximation to Fermi's golden rule. The contribution of individual scattering rates is analyzed as a function of 2D electron density as well as of alloy composition in MoxW1-xS2. While impurity scattering limits the mobility for low carrier densities (<2-4x10(12) cm(-2)), LO polar phonon scattering is the dominant mechanism for high electron densities. Alloy scattering is found to play a non-negligible role for 0.5 < x < 0.7 in MoxW1-xS2. The LO phonon-limited and impurity-limited mobilities show opposing trends with respect to alloy mole fractions. The understanding of electron mobility in MoxW1-xS2 presented here is expected to enable the design and realization of heterostructures and devices based on alloys of MoS2 andWS(2).

Accelerating method of moments based package-board 3D parasitic extraction using FPGA

In this article, a Field Programmable Gate Array (FPGA)-based hardware accelerator for 3D electromagnetic extraction, using Method of Moments (MoM) is presented. As the number of nets or ports in a system increases, leading to a corresponding increase in the number of right-hand-side (RHS) vectors, the computational cost for multiple matrix-vector products presents a time bottleneck in a linear-complexity fast solver framework. In this work, an FPGA-based hardware implementation is proposed toward a two-level parallelization scheme: (i) matrix level parallelization for single RHS and (ii) pipelining for multiple-RHS. The method is applied to accelerate electrostatic parasitic capacitance extraction of multiple nets in a Ball Grid Array (BGA) package. The acceleration is shown to be linearly scalable with FPGA resources and speed-ups over 10x against equivalent software implementation on a 2.4GHz Intel Core i5 processor is achieved using a Virtex-6 XC6VLX240T FPGA on Xilinx's ML605 board with the implemented design operating at 200MHz clock frequency. (c) 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:776-783, 2016