A Compact Defected Ground Microstrip Device with Photonic Bandgap Effects

Filters and other devices using photonic bandgap (PBG) theory are typically implemented in microstrip lines by etching periodic holes on the ground plane of the microstrip. The period of such several holes corresponds to nearly half the guided wavelength of the transmission line. In this paper we study the effects of miniaturization of the PBG device by meandering the microstrip line about one single hole in the ground plane. A comparison of the S-parameters and dispersion behavior of the modified geometry and a conventional PBG device with a straight microstrip line shows that these devices have similar behaviors.

Surface instability of confined elastic bilayers: Theory and simulations

The surface of a soft elastic film becomes unstable and forms a self-organized undulating pattern because of adhesive interactions when it comes in contact proximity with a rigid surface. For a single film, the pattern length scale lambda, which is governed by the minimization of the elastic stored energy, gives lambda similar to 3h, where h is the film thickness. Based on a linear stability analysis and simulations of adhesion and debonding, we consider the contact instability of an elastic bilayer, which provides greater flexibility in the morphological control of interfacial instability. Unlike the case of a single film, the morphology of the contact instability patterns, debonding distance, and debonding force in a bilayer can be controlled in a nonlinear way by varying the thicknesses and shear moduli of the films. Interestingly, the pattern wavelength in a bilayer can be greatly increased or decreased compared to a single film when the adhesive contact is formed by the stiffer or the softer of the two films, respectively. In particular, lambda as small as 0.5h can be obtained. This indicates a new strategy for pattern miniaturization in elastic contact lithography.

Studies on design, fabrication and reliability assessment of embedded passives on a high-density interconnect (HDI) organic substrate using a sequential build-up process

One of the foremost design considerations in microelectronics miniaturization is the use of embedded passives which provide practical solution. In a typical circuit, over 80 percent of the electronic components are passives such as resistors, inductors, and capacitors that could take up to almost 50 percent of the entire printed circuit board area. By integrating passive components within the substrate instead of being on the surface, embedded passives reduce the system real estate, eliminate the need for discrete and assembly, enhance electrical performance and reliability, and potentially reduce the overall cost. Moreover, it is lead free. Even with these advantages, embedded passive technology is at a relatively immature stage and more characterization and optimization are needed for practical applications leading to its commercialization.This paper presents an entire process from design and fabrication to electrical characterization and reliability test of embedded passives on multilayered microvia organic substrate. Two test vehicles focusing on resistors and capacitors have been designed and fabricated. Embedded capacitors in this study are made with polymer/ceramic nanocomposite (BaTiO3) material to take advantage of low processing temperature of polymers and relatively high dielectric constant of ceramics and the values of these capacitors range from 50 pF to 1.5 nF with capacitance per area of approximately 1.5 nF/cm(2). Limited high frequency measurement of these capacitors was performed. Furthermore, reliability assessments of thermal shock and temperature humidity tests based on JEDEC standards were carried out. Resistors used in this work have been of three types: 1) carbon ink based polymer thick film (PTF), 2) resistor foils with known sheet resistivities which are laminated to printed wiring board (PWB) during a sequential build-up (SBU) process and 3) thin-film resistor plating by electroless method. Realization of embedded resistors on conventional board-level high-loss epoxy (similar to 0.015 at 1 GHz) and proposed low-loss BCB dielectric (similar to 0.0008 at > 40 GHz) has been explored in this study. Ni-P and Ni-W-P alloys were plated using conventional electroless plating, and NiCr and NiCrAlSi foils were used for the foil transfer process. For the first time, Benzocyclobutene (BCB) has been proposed as a board level dielectric for advanced System-on-Package (SOP) module primarily due to its attractive low-loss (for RF application) and thin film (for high density wiring) properties.Although embedded passives are more reliable by eliminating solder joint interconnects, they also introduce other concerns such as cracks, delamination and component instability. More layers may be needed to accommodate the embedded passives, and various materials within the substrate may cause significant thermo -mechanical stress due to coefficient of thermal expansion (CTE) mismatch. In this work, numerical models of embedded capacitors have been developed to qualitatively examine the effects of process conditions and electrical performance due to thermo-mechanical deformations.Also, a prototype working product with the board level design including features of embedded resistors and capacitors are underway. Preliminary results of these are presented.

Compiler Assisted Leakage Energy Optimization for Clustered VLIW Architectures

Miniaturization of devices and the ensuing decrease in the threshold voltage has led to a substantial increase in the leakage component of the total processor energy consumption. Relatively simpler issue logic and the presence of a large number of function units in the VLIW and the clustered VLIW architectures attribute a large fraction of this leakage energy consumption in the functional units. However, functional units are not fully utilized in the VLIW architectures because of the inherent variations in the ILP of the programs. This underutilization is even more pronounced in the context of clustered VLIW architectures because of the contentions for the limited number of slow intercluster communication channels which lead to many short idle cycles.In the past, some architectural schemes have been proposed to obtain leakage energy bene .ts by aggressively exploiting the idleness of functional units. However, presence of many short idle cycles cause frequent transitions from the active mode to the sleep mode and vice-versa and adversely a ffects the energy benefits of a purely hardware based scheme. In this paper, we propose and evaluate a compiler instruction scheduling algorithm that assist such a hardware based scheme in the context of VLIW and clustered VLIW architectures. The proposed scheme exploits the scheduling slacks of instructions to orchestrate the functional unit mapping with the objective of reducing the number of transitions in functional units thereby keeping them off for a longer duration. The proposed compiler-assisted scheme obtains a further 12% reduction of energy consumption of functional units with negligible performance degradation over a hardware-only scheme for a VLIW architecture. The benefits are 15% and 17% in the context of a 2-clustered and a 4-clustered VLIW architecture respectively. Our test bed uses the Trimaran compiler infrastructure.

Analysis of non-uniform waveguide in MZI and optimization of the power confinement in the waveguide

The technological world has attained a new dimension with the advent of miniaturization and a major breakthrough has evolved in the form of moems, technically more advanced than mems. This breakthrough has paved way for the scientists to research and conceive their innovation. This paper presents a mathematical analysis of the wave propagation along the non-uniform waveguide with refractive index varying along the z axis implemented on the cantilever beam of MZI based moem accelerometer. Secondly the studies on the wave bends with minimum power loss focusing on two main aspects of bend angle and curvature angle is also presented.

Demonstration of a microfluidic polarimeter

Traditional methods of detecting chiral molecules, such as optical rotation are not suitable for miniaturization, since, the magnitude of the rotation of polarization scales down linearly with the optical path length of the device. Since the origin of optical activity is due to difference of refractive indices between the two circularly polarized states of light, it is possible to detect chiral media by measuring the dependence of the angles of refraction on the polarization state of the incident light. This however is a weak effect and hence requires sensitive optical detection schemes, based on novel polarization modulation techniques. The device can be scaled down for applications involving small sample volumes. Fabrication details of a prototype microfluidic device are described.

Compiler-assisted energy optimization for clustered VLIW processors

Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving the clock speed, reducing the energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. This communication happens over long global wires having high load capacitance which leads to delay in execution and significantly high energy consumption. Inter-cluster communication also introduces many short idle cycles, thereby significantly increasing the overall leakage energy consumption in the functional units. The trend towards miniaturization of devices (and associated reduction in threshold voltage) makes energy consumption in interconnects and functional units even worse, and limits the usability of clustered architectures in smaller technologies. However, technological advancements now permit the design of interconnects and functional units with varying performance and power modes. In this paper, we propose scheduling algorithms that aggregate the scheduling slack of instructions and communication slack of data values to exploit the low-power modes of functional units and interconnects. Finally, we present a synergistic combination of these algorithms that simultaneously saves energy in functional units and interconnects to improves the usability of clustered architectures by achieving better overall energy-performance trade-offs. Even with conservative estimates of the contribution of the functional units and interconnects to the overall processor energy consumption, the proposed combined scheme obtains on average 8% and 10% improvement in overall energy-delay product with 3.5% and 2% performance degradation for a 2-clustered and a 4-clustered machine, respectively. We present a detailed experimental evaluation of the proposed schemes. Our test bed uses the Trimaran compiler infrastructure. (C) 2012 Elsevier Inc. All rights reserved.

Low-thermal-budget solution processing of thin films of zinc ferrite and other complex oxides

Further miniaturization of magnetic and electronic devices demands thin films of advanced nanomaterials with unique properties. Spinel ferrites have been studied extensively owing to their interesting magnetic and electrical properties coupled with stability against oxidation. Being an important ferrospinel, zinc ferrite has wide applications in the biological (MRI) and electronics (RF-CMOS) arenas. The performance of an oxide like ZnFe2O4 depends on stoichiometry (defect structure), and technological applications require thin films of high density, low porosity and controlled microstructure, which depend on the preparation process. While there are many methods for the synthesis of polycrystalline ZnFe2O4 powder, few methods exist for the deposition of its thin films, where prolonged processing at elevated temperature is not required. We report a novel, microwave-assisted, low temperature (<100°C) deposition process that is conducted in the liquid medium, developed for obtaining high quality, polycrystalline ZnFe2O4 thin films on technologically important substrates like Si(100). An environment-friendly solvent (ethanol) and non-hazardous oxide precursors (β-diketonates of Zn and Fe in 1:2 molar ratio), forming a solution together, is subjected to irradiation in a domestic microwave oven (2.45 GHz) for a few minutes, leading to reactions which result in the deposition of ZnFe2O4 films on Si (100) substrates suspended in the solution. Selected surfactants added to the reactant solution in optimum concentration can be used to control film microstructure. The nominal temperature of the irradiated solution, i.e., film deposition temperature, seldom exceeds 100°C, thus sharply lowering the thermal budget. Surface roughness and uniformity of large area depositions (50x50 mm2) are controlled by tweaking the concentration of the mother solution. Thickness of the films thus grown on Si (100) within 5 min of microwave irradiation can be as high as several microns. The present process, not requiring a vacuum system, carries a very low thermal budget and, together with a proper choice of solvents, is compatible with CMOS integration. This novel solution-based process for depositing highly resistive, adherent, smooth ferrimagnetic films on Si (100) is promising to RF engineers for the fabrication of passive circuit components. It is readily extended to a wide variety of functional oxide films.

CMOS-Compatible and Scalable Deposition of Nanocrystalline Zinc Ferrite Thin Film to Improve Inductance Density of Integrated RF Inductor

Development towards the combination of miniaturization and improved functionality of RFIC has been stalled due to the lack of high-performance integrated inductors. To meet this challenge, integration of magnetic material with high permeability as well as low conductivity is a must. Ferrite films are excellent candidates for RF devices due to their low cost, high resistivity, and low eddy current losses. Unlike its bulk counterpart, nanocrystalline zinc ferrite, because of partial inversion in the spinel structure, exhibits novel magnetic properties suitable for RF applications. However, most scalable ferrite film deposition processes require either high temperature or expensive equipment or both. We report a novel low temperature (< 200 degrees C) solution-based deposition process for obtaining high quality, polycrystalline zinc ferrite thin films (ZFTF) on Si (100) and on CMOS-foundry-fabricated spiral inductor structures, rapidly, using safe solvents and precursors. An enhancement of up to 20% at 5 GHz in the inductance of a fabricated device was achieved due to the deposited ZFTF. Substantial inductance enhancement requires sufficiently thick films and our reported process is capable of depositing smooth, uniform films as thick as similar to 20 mu m just by altering the solution composition. The method is capable of depositing film conformally on a surface with complex geometry. As it requires neither a vacuum system nor any post-deposition processing, the method reported here has a low thermal budget, making it compatible with modern CMOS process flow.

Small-scale mechanical testing of materials

Small-scale mechanical testing of materials has gained prominence in the last decade or so due to the continuous miniaturization of components and devices in everyday application. This review describes the various micro-fabrication processes associated with the preparation of miniaturized specimens, geometries of test specimens and the small scale testing techniques used to determine the mechanical behaviour of materials at the length scales of a few hundred micro-meters and below. This is followed by illustrative examples in a selected class of materials. The choice of the case studies is based on the relevance of the materials used in today's world: evaluation of mechanical properties of thermal barrier coatings (TBCs), applied for enhanced high temperature protection of advanced gas turbine engine components, is essential since its failure by fracture leads to the collapse of the engine system. Si-based substrates, though brittle, are indispensible for MEMS/NEMS applications. Biological specimens, whose response to mechanical loads is important to ascertain their role in diseases and to mimic their structure for attaining high fracture toughness and impact resistance. An insight into the mechanisms behind the observed size effects in metallic systems can be exploited to achieve excellent strength at the nano-scale. A future outlook of where all this is heading is also presented.

ABOUT FORMS OF ELECTRONIC AND IONIC DEVICES WITH THERMIONIC CATHODES.

The miniaturization of electronic and ionic devices with thermionic cathodes and thc improvement of their vacuum properties are questions of very great interest to the electronic engineer. However there have bcen no proposals so far to analyse the problem of miniaturization of such devices In a fundamental way. The present work suggests a choice of the geometrical shape of the cathode, the anode and the envelope of the device, that may help towards such a fundamcnlal approach.It is shown that a design, in which the cathode and the envelope of the tube are made of thm prismatic shape and the anode coincides with the cnvclope, offers a slriknrg advantage over the conventional cylindrical design, in respect of over-all size. The use of the prismatic shape will lead to considerable economy in msterials and may facilitate simpler prodoct~ont echn~ques. I n respect of the miin criteria of vacuum, namely the grade of vacuum, the internal volume occupied by residual gases, the evolution of gases in the internal space and the diffusion of gases from outside into the devicc, it is shown that the prismatic form is at least as good as, if not somewhat superior lo, the cylindrical form.In the actual construction of thin prismatic tubes, manv practical problems will arise, the most important being the mechanical strength and stablity of the structure. But the changeover from the conventional cylindrical to the new prirmaiic form, with its basic advantages, is a development that merits close attention.

Design and analysis of integrated optic quadrature phase shift keying modulator

Quadrature phase shift keying (QPSK) is one of the most popular modulation schemes in coherent optical communication systems for data rates in excess of 40 Gbps because of its high spectral efficiency. This paper proposes a simple method of implementing a QPSK modulator in integrated optic (IO) domain. The QPSK modulator is realized using standard IO components, such as Y-branches and electro-optic modulators (EOMs). Design optimization of EOM is carried out considering the fabrication constraints, miniaturization aspects, and simplicity. Also, the interdependency between electrode length, operating voltage, and electrode gap of an EOM has been captured in the form of a family of curves. These plots enable designing of EOMs for custom requirements. An innovative approach has been adopted in demonstrating the operation of IO QPSK modulator in terms of phase data extracted from beam propagation model. The results obtained by this approach have been verified using the conventional interferometric approach. The operation of the proposed IO QPSK modulator is experimentally demonstrated. The design of IO QPSK modulator is taken up as a part of a broader scheme that aims at generation of QPSK modulated microwave signal based on optical heterodyning. (C) 2014 Society of Photo-Optical Instrumentation Engineers (SPIE)