Ground Plane Slot Structures for Isolation of Cosited Microstrip Antennas

Ground plane slot structures have been shown to reduce coupling between cosited antennas. Although some such structures have already been reported, no analytical model exists to describe their behavior and there are no design guidelines. In this work, the behavior of reported ground plane structures is used as a clue to obtain generalizable information about such structures' behavior. The structures' scalability and excitation behavior is investigated. Next a circuit model is derived that describes the interaction of microstrip patch antennas with a ground plane slot structure based on mutual admittances between the ground plane slots and the effective slots at the antennas' radiating edges. The circuit model leads to design guidelines for the ground plane slot structure and an approximate relationship between mutual admittances which must be satisfied in order to isolate the antennas. Finally, we present a novel ground plane slot structure that mitigates some of the disadvantages of earlier designs.

Growth and application of planar III-V semiconductor nanowires grown with MOCVD

The semiconductor nanowire has been widely studied over the past decade and identified as a promising nanotechnology building block with application in photonics and electronics. The flexible bottom-up approach to nanowire growth allows for straightforward fabrication of complex 1D nanostructures with interesting optical, electrical, and mechanical properties. III-V nanowires in particular are useful because of their direct bandgap, high carrier mobility, and ability to form heterojunctions and have been used to make devices such as light-emitting diodes, lasers, and field-effect transistors. However, crystal defects are widely reported for III-V nanowires when grown in the common out-of-plane <111>B direction. Furthermore, commercialization of nanowires has been limited by the difficulty of assembling nanowires with predetermined position and alignment on a wafer-scale. In this thesis, planar III-V nanowires are introduced as a low-defect and integratable nanotechnology building block grown with metalorganic chemical vapor deposition. Planar GaAs nanowires grown with gold seed particles self-align along the <110> direction on the (001) GaAs substrate. Transmission electron microscopy reveals that planar GaAs nanowires are nearly free of crystal defects and grow laterally and epitaxially on the substrate surface. The nanowire morphology is shown to be primarily controlled through growth temperature and an ideal growth window of 470 +\- 10 °C is identified for planar GaAs nanowires. Extension of the planar growth mode to other materials is demonstrated through growth of planar InAs nanowires. Using a sacrificial layer, the transfer of planar GaAs nanowires onto silicon substrates with control over the alignment and position is presented. A metal-semiconductor field-effect transistor fabricated with a planar GaAs nanowire shows bulk-like low-field electron transport characteristics with high mobility. The aligned planar geometry and excellent material quality of planar III-V nanowires may lead to highly integrated III-V nanophotonics and nanoelectronics.