2 resultados para Semiconductor surface

em Illinois Digital Environment for Access to Learning and Scholarship Repository


Relevância:

30.00% 30.00%

Publicador:

Resumo:

The semiconductor nanowire has been widely studied over the past decade and identified as a promising nanotechnology building block with application in photonics and electronics. The flexible bottom-up approach to nanowire growth allows for straightforward fabrication of complex 1D nanostructures with interesting optical, electrical, and mechanical properties. III-V nanowires in particular are useful because of their direct bandgap, high carrier mobility, and ability to form heterojunctions and have been used to make devices such as light-emitting diodes, lasers, and field-effect transistors. However, crystal defects are widely reported for III-V nanowires when grown in the common out-of-plane <111>B direction. Furthermore, commercialization of nanowires has been limited by the difficulty of assembling nanowires with predetermined position and alignment on a wafer-scale. In this thesis, planar III-V nanowires are introduced as a low-defect and integratable nanotechnology building block grown with metalorganic chemical vapor deposition. Planar GaAs nanowires grown with gold seed particles self-align along the <110> direction on the (001) GaAs substrate. Transmission electron microscopy reveals that planar GaAs nanowires are nearly free of crystal defects and grow laterally and epitaxially on the substrate surface. The nanowire morphology is shown to be primarily controlled through growth temperature and an ideal growth window of 470 +\- 10 °C is identified for planar GaAs nanowires. Extension of the planar growth mode to other materials is demonstrated through growth of planar InAs nanowires. Using a sacrificial layer, the transfer of planar GaAs nanowires onto silicon substrates with control over the alignment and position is presented. A metal-semiconductor field-effect transistor fabricated with a planar GaAs nanowire shows bulk-like low-field electron transport characteristics with high mobility. The aligned planar geometry and excellent material quality of planar III-V nanowires may lead to highly integrated III-V nanophotonics and nanoelectronics.

Relevância:

30.00% 30.00%

Publicador:

Resumo:

Photoemission techniques, utilizing a synchrotron light source, were used to analyze the clean (100) surfaces of the zinc-blende semiconductor materials CdTe and InSb. Several interfacial systems involving the surfaces of these materials were also studied, including the CdTe(lOO)-Ag interface, the CdTe(lOO)-Sb system, and the InSb(lOO)-Sn interface. High-energy electron diffraction was also employed to acquire information about of surface structure. A one-domain (2xl) structure was observed for the CdTe(lOO) surface. Analysis of photoemission spectra of the Cd 4d core level for this surface structure revealed two components resulting from Cd surface atoms. The total intensity of these components accounts for a full monolayer of Cd atoms on the surface. A structural model is discussed commensurate with these results. Photoemission spectra of the Cd and Te 4d core levels indicate that Ag or Sb deposited on the CdTe(l00)-(2xl) surface at room temperature do not bound strongly to the surface Cd atoms. The room temperature growth characteristics for these two elements on the CdTe(lOO)-(2xl) are discussed. The growth at elevated substrate temperatures was also studied for Sb deposition. The InSb(lOO) surface differed from the CdTe(lOO) surface. Using molecular beam epitaxy, several structures could be generated for the InSb(lOO) surface, including a c(8x2), a c(4x4), an asymmetric (lx3), a symmetric (lx3), and a (lxl). Analysis of photoemission intensities and line shapes indicates that the c(4x4) surface is terminated with 1-3/4 monolayers of Sb atoms. The c(8x2) surface is found to be terminated with 3/4 monolayer of In atoms. Structural models for both of these surfaces are proposed based upon the photoemission results and upon models of the similar GaAs(lOO) structures. The room temperature growth characteristics of grey Sn on the lnSb(lOO)-c(4x4) and InSb(l00)-c(8x2) surfaces were studied with photoemission. The discontinuity in the valence band maximum for this semiconductor heterojunction system is measured to be 0.40 eV, independent of the starting surface structure and stoichiometry. This result is reconciled with theoretical predictions for heterostructure behavior.