Design of advanced reverse osmosis and nanofiltration membranes for water purification

Most commercially available reverse osmosis (RO) and nanofiltration (NF) membranes are based on the thin film composite (TFC) aromatic polyamide membranes. However, they have several disadvantages including low resistance to fouling, low chemical and thermal stabilities and limited chlorine tolerance. To address these problems, advanced RO/NF membranes are being developed from polyimides for water and wastewater treatments. The following three projects have resulted from my research. (1) Positively charged and solvent resistant NF membranes. The use of solvent resistant membranes to facilitate small molecule separations has been a long standing industry goal of the chemical and pharmaceutical industries. We developed a solvent resistant membrane by chemically cross-linking of polyimide membrane using polyethylenimine. This membrane showed excellent stability in almost all organic solvents. In addition, this membrane was positively charged due to the amine groups remaining on the surface. As a result, high efficiency (> 95%) and selectivity for multivalent heavy metal removal was achieved. (2) Fouling resistant NF membranes. Antifouling membranes are highly desired for “all” applications because fouling will lead to higher energy demand, increase of cleaning and corresponding down time and reduced life-time of the membrane elements. For fouling prevention, we designed a new membrane system using a coating technique to modify membrane surface properties to avoid adsorption of foulants like humic acid. A layer of water-soluble polymer such as polyvinyl alcohol (PVA), polyacrylic acid (PAA), polyvinyl sulfate (PVS) or sulfonated poly(ether ether ketone) (SPEEK), was adsorbed onto the surface of a positively charged membrane. The resultant membranes have a smooth and almost neutrally charged surface which showed better fouling resistance than both the positively charged NF membranes and commercially available negatively charged NTR-7450 membrane. In addition, these membranes showed high efficiency for removal of multivalent ions (> 95% for both cations and anions). Therefore, these antifouling surfaces can be potentially used for water softening, water desalination and wastewater treatment in a membrane bioreactor (MBR) process. (3) Thermally stable RO membranes. Commercial RO membranes cannot be used at temperature higher than 45°C due to the use of polysulfone substrate, which often limits their applications in industries. We successfully developed polyimides as the membrane substrate for thermally stable RO membranes due to their high thermal resistance. The polyimide-based composite polyamide membranes showed desalination performance comparable to the commercial TFC membrane. However, the key advantage of the polyimide-based membrane is its high thermal stability. As the feed temperature increased from 25oC to 95oC, the water flux increased 5 - 6 times while the salt rejection almost kept constant. This membrane appears to provide a unique solution for hot water desalination and also a feasible way to improve the water productivity by increasing the operating temperature without any drop in salt rejection.

Low-power high-performance SAR ADC design with digital calibration techniques

This dissertation presents the design of three high-performance successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized code-domain linear equalizer. These digital calibration techniques effectively and efficiently remove the static mismatch errors in the analog-to-digital (A/D) conversion. They enable aggressive scaling of the capacitive digital-to-analog converter (DAC), which also serves as sampling capacitor, to the kT/C limit. As a result, outstanding conversion linearity, high signal-to-noise ratio (SNR), high conversion speed, robustness, superb energy efficiency, and minimal chip-area are accomplished simultaneously. The first design is a 12-bit 22.5/45-MS/s SAR ADC in 0.13-μm CMOS process. It employs a perturbation-based calibration based on the superposition property of linear systems to digitally correct the capacitor mismatch error in the weighted DAC. With 3.0-mW power dissipation at a 1.2-V power supply and a 22.5-MS/s sample rate, it achieves a 71.1-dB signal-to-noise-plus-distortion ratio (SNDR), and a 94.6-dB spurious free dynamic range (SFDR). At Nyquist frequency, the conversion figure of merit (FoM) is 50.8 fJ/conversion step, the best FoM up to date (2010) for 12-bit ADCs. The SAR ADC core occupies 0.06 mm2, while the estimated area the calibration circuits is 0.03 mm2. The second proposed digital calibration technique is a bit-wise-correlation-based digital calibration. It utilizes the statistical independence of an injected pseudo-random signal and the input signal to correct the DAC mismatch in SAR ADCs. This idea is experimentally verified in a 12-bit 37-MS/s SAR ADC fabricated in 65-nm CMOS implemented by Pingli Huang. This prototype chip achieves a 70.23-dB peak SNDR and an 81.02-dB peak SFDR, while occupying 0.12-mm2 silicon area and dissipating 9.14 mW from a 1.2-V supply with the synthesized digital calibration circuits included. The third work is an 8-bit, 600-MS/s, 10-way time-interleaved SAR ADC array fabricated in 0.13-μm CMOS process. This work employs an adaptive digital equalization approach to calibrate both intra-channel nonlinearities and inter-channel mismatch errors. The prototype chip achieves 47.4-dB SNDR, 63.6-dB SFDR, less than 0.30-LSB differential nonlinearity (DNL), and less than 0.23-LSB integral nonlinearity (INL). The ADC array occupies an active area of 1.35 mm2 and dissipates 30.3 mW, including synthesized digital calibration circuits and an on-chip dual-loop delay-locked loop (DLL) for clock generation and synchronization.