Modelling the development of an online learning resource by health care professionals

The aim of this study was to model the process of development for an Online Learning Resource (OLR) by Health Care Professionals (HCPs) to meet lymphoedema-related educational needs, within an asset-based management context. Previous research has shown that HCPs have unmet educational needs in relation to lymphoedema but details on their specific nature or context were lacking. Against this background, the study was conducted in two distinct but complementary phases. In Phase 1, a national survey was conducted of HCPs predominantly in community, oncology and palliative care services, followed by focus group discussions with a sample of respondents. In Phase 2, lymphoedema specialists (LSs) used an action research approach to design and implement an OLR to meet the needs identified in Phase 1. Study findings were analysed using descriptive statistics (Phase 1), and framework, thematic and dialectic analysis to explore their potential to inform future service development and education theory. Unmet educational need was found to be specific to health care setting and professional group. These resulted in HCPs feeling poorly-equipped to diagnose and manage lymphoedema. Of concern, when identified, lymphoedema was sometimes buried for fear of overwhelming stretched services. An OLR was identified as a means of addressing the unmet educational needs. This was successfully developed and implemented with minimal additional resources. The process model created has the potential to inform contemporary leadership theory in asset-based management contexts. This doctoral research makes a timely contribution to leadership theory since the resource constraints underpinning much of the contribution has salience to current public services. The process model created has the potential to inform contemporary leadership theory in asset-based management contexts. Further study of a leadership style which incorporates cognisance of Cognitive Load Theory and Self-Determination Theory is suggested. In addition, the detailed reporting of process and how this facilitated learning for participants contributes to workplace education theory

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.