High performance terahertz resonant tunnelling diode sources and broadband antenna for air-side radiation

Resonant tunnelling diode (RTD) is known to be the fastest electronics device that can be fabricated in compact form and operate at room temperature with potential oscillation frequency up to 2.5 THz. The RTD device consists of a narrow band gap quantum well layer sandwiched between two thin wide band gap barriers layers. It exhibits negative differential resistance (NDR) region in its current-voltage (I-V) characteristics which is utilised in making oscillators. Up to date, the main challenge is producing high output power at high frequencies in particular. Although oscillation frequencies of ~ 2 THz have been already reported, the output power is in the range of micro-Watts. This thesis describes the systematic work on the design, fabrication, and characterisation of RTD-based oscillators in microwave/millimetre-wave monolithic integrated circuits (MMIC) form that can produce high output power and high oscillation frequency at the same time. Different MMIC RTD oscillator topologies were designed, fabricated, and characterised in this project which include: single RTD oscillator which employs one RTD device, double RTDs oscillator which employs two RTD devices connected in parallel, and coupled RTD oscillators which combine the powers of two oscillators over a single load, based on mutual coupling and which can employ up to four RTD devices. All oscillators employed relatively large size RTD devices for high power operation. The main challenge was to realise high oscillation frequency (~ 300 GHz) in MMIC form with the employed large sized RTD devices. To achieve this aim, proper designs of passive structures that can provide small values of resonating inductances were essential. These resonating inductance structures included shorted coplanar wave guide (CPW) and shorted microstrip transmission lines of low characteristics impedances Zo. Shorted transmission line of lower Zo has lower inductance per unit length. Thus, the geometrical dimensions would be relatively large and facilitate fabrication by low cost photolithography. A series of oscillators with oscillation frequencies in the J-band (220 – 325 GHz) range and output powers from 0.2 – 1.1 mW have been achieved in this project, and all were fabricated using photolithography. Theoretical estimation showed that higher oscillation frequencies (> 1 THz) can be achieved with the proposed MMIC RTD oscillators design in this project using photolithography with expected high power operation. Besides MMIC RTD oscillators, reported planar antennas for RTD-based oscillators were critically reviewed and the main challenges in designing high performance integrated antennas on large dielectric constant substrates are discussed in this thesis. A novel antenna was designed, simulated, fabricated, and characterised in this project. It was a bow-tie antenna with a tuning stub that has very wide bandwidth across the J-band. The antenna was diced and mounted on a reflector ground plane to alleviate the effect of the large dielectric constant substrate (InP) and radiates upwards to the air-side direction. The antenna was also investigated for integration with the all types of oscillators realised in this project. One port and two port antennas were designed, simulated, fabricated, and characterised and showed the suitability of integration with the single/double oscillator layout and the coupled oscillator layout, respectively.

The development of planar high-K/III-V p-channel MOSFETs for post-silicon CMOS

Conventional Si complementary-metal-oxide-semiconductor (CMOS) scaling is fast approaching its limits. The extension of the logic device roadmap for future enhancements in transistor performance requires non-Si materials and new device architectures. III-V materials, due to their superior electron transport properties, are well poised to replace Si as the channel material beyond the 10nm technology node to mitigate the performance loss of Si transistors from further reductions in supply voltage to minimise power dissipation in logic circuits. However several key challenges, including a high quality dielectric/III-V gate stack, a low-resistance source/drain (S/D) technology, heterointegration onto a Si platform and a viable III-V p-metal-oxide-semiconductor field-effect-transistor (MOSFET), need to be addressed before III-Vs can be employed in CMOS. This Thesis specifically addressed the development and demonstration of planar III-V p-MOSFETs, to complement the n-MOSFET, thereby enabling an all III-V CMOS technology to be realised. This work explored the application of InGaAs and InGaSb material systems as the channel, in conjunction with Al2O3/metal gate stacks, for p-MOSFET development based on the buried-channel flatband device architecture. The body of work undertaken comprised material development, process module development and integration into a robust fabrication flow for the demonstration of p-channel devices. The parameter space in the design of the device layer structure, based around the III-V channel/barrier material options of In_x≥0.53Ga_1-xAs/In_0.52Al_0.48As and In_x≥0.1Ga_1-xSb/AlSb, was systematically examined to improve hole channel transport. A mobility of 433 cm²/Vs, the highest room temperature hole mobility of any InGaAs quantum-well channel reported to date, was obtained for the In_0.85Ga_0.15As (2.1% strain) structure. S/D ohmic contacts were developed based on thermally annealed Au/Zn/Au metallisation and validated using transmission line model test structures. The effects of metallisation thickness, diffusion barriers and de-oxidation conditions were examined. Contacts to InGaSb-channel structures were found to be sensitive to de-oxidation conditions. A fabrication process, based on a lithographically-aligned double ohmic patterning approach, was realised for deep submicron gate-to-source/drain gap (L_side) scaling to minimise the access resistance, thereby mitigating the effects of parasitic S/D series resistance on transistor performance. The developed process yielded gaps as small as 20nm. For high-k integration on GaSb, ex-situ ammonium sulphide ((NH₄)₂S) treatments, in the range 1%-22%, for 10min at 295K were systematically explored for improving the electrical properties of the Al₂O₃/GaSb interface. Electrical and physical characterisation indicated the 1% treatment to be most effective with interface trap densities in the range of 4 - 10×10¹²cm^-2eV^-1 in the lower half of the bandgap. An extended study, comprising additional immersion times at each sulphide concentration, was further undertaken to determine the surface roughness and the etching nature of the treatments on GaSb. A number of p-MOSFETs based on III-V-channels with the most promising hole transport and integration of the developed process modules were successfully demonstrated in this work. Although the non-inverted InGaAs-channel devices showed good current modulation and switch-off characteristics, several aspects of performance were non-ideal; depletion-mode operation, modest drive current (I_d,sat=1.14mA/mm), double peaked transconductance (g_m=1.06mS/mm), high subthreshold swing (SS=301mV/dec) and high on-resistance (R_on=845kΩ.μm). Despite demonstrating substantial improvement in the on-state metrics of I_d,sat (11×), g_m (5.5×) and R_on (5.6×), inverted devices did not switch-off. Scaling gate-to-source/drain gap (L_side) from 1μm down to 70nm improved I_d,sat (72.4mA/mm) by a factor of 3.6 and gm (25.8mS/mm) by a factor of 4.1 in inverted InGaAs-channel devices. Well-controlled current modulation and good saturation behaviour was observed for InGaSb-channel devices. In the on-state In_0.3Ga_0.7Sb-channel (I_d,sat=49.4mA/mm, g_m=12.3mS/mm, R_on=31.7kΩ.μm) and In_0.4Ga_0.6Sb-channel (I_d,sat=38mA/mm, g_m=11.9mS/mm, R_on=73.5kΩ.μm) devices outperformed the InGaAs-channel devices. However the devices could not be switched off. These findings indicate that III-V p-MOSFETs based on InGaSb as opposed to InGaAs channels are more suited as the p-channel option for post-Si CMOS.