Deindustrialisation and industrial communities: the Lanarkshire coalfields c.1947-1983

This thesis examines deindustrialisation, the declining contribution of industrial activities to economic output and employment, in Lanarkshire, Scotland’s largest coalfield between the early nineteenth and mid-twentieth century. It focuses on contraction between the National Coal Board’s (NCB) vesting in 1947 and the closure of Lanarkshire’s last colliery, Cardowan, in 1983. Deindustrialisation was not the natural outcome of either market forces or geological exhaustion. Colliery closures and falling coal employment were the result of policy-makers’ decisions. The thesis consists of four thematic chapters: political economy, moral economy, class and community, and generation and gender. The analysis is based on archival sources including Scottish Office reports and correspondence relating to regional policy, and NCB records. These are supported by National Union of Mineworkers Scottish Area and STUC meeting minutes, and oral history testimonies from over 30 men and women with Lanarkshire coalfield backgrounds, as well as two focus groups. The first two chapters analyse the process of deindustrialisation, with the first offering a top-down perspective and the second a bottom-up viewpoint. In chapter one deindustrialisation is analysed through changes in political economy. Shifts in labour market structure are examined through the development of regional policy and its administration by the Scottish Office. The analysis centres upon a policy network of Scottish business elites and civil servants who shaped a vision of modernisation via industrial diversification through attracting inward investment. In chapter two the perspective shifts to community and workforce. It analyses responses to coalfield contraction through a moral economy of customary rights to colliery employment. A detailed investigation of Lanarkshire colliery closures between the 1940s and 1980s emphasises the protracted nature of deindustrialisation. Chapters three and four consider the social and cultural structures which shaped the moral economy but were heavily altered by deindustrialisation. Chapter three focuses on the dense networks that linked occupation, community, and class consciousness. Increasing coalfield centralisation and remote control of pits from NCB headquarters in London, and mounting hostility to coal closures, contributed to an accentuated sense of Scottish-ness. Chapter four illuminates gender and generational dimensions. The differing experiences of cohorts of men who faced either early retirement, redundancy or transfer to alternative sectors, or those who never attained anticipated industrial employment due to final closures, are analysed in terms of constructions of masculinity and the endurance of cultural as well as material losses. This is counterpoised to women who gained industrial work in assembly plants and the perceived gradual attainment of an improved economic and social position whilst continuing to navigate structures of patriarchy.

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.