Improving interfaces for nerve repair

Autologous nerve grafts are the current gold standard for the repair of peripheral nerve injuries. However, there is a need to develop an alternative to this technique, as donor-site morbidities such as neuroma formation and permanent loss of function are a few of the limitations concerned with this technique. Artificial nerve conduits have therefore emerged as an alternative for the repair of short peripheral nerve defects of less than 30 mm, however they do not surpass autologous nerve grafts clinically. To develop a nerve conduit that supports regeneration over long nerve gaps and in large diameter nerves, researchers have focused on functionalizing of the conduits by studying the components that enhance nerve regeneration such as micro/nano-topography, growth factor delivery systems, supportive cells and extracellular matrix (ECM) proteins as well as understanding the complex biological reactions that take place during peripheral nerve regeneration. This thesis presents strategies to improve peripheral nerve interfaces to better the regenerative potential by using dorsal root ganglions (DRGs) isolated from neonatal rats as an in vitro model of nerve regeneration. The work started off by investigating the usefulness of a frog foam protein Ranaspumin-2 (Rsn2) to coat biomaterials for compatibility, this lead to the discovery of temporary cell adhesion on polydimethylsiloxane (PDMS), which was investigated as a suitable tool to derive cell-sheets for nerve repair. The influence of Rsn2 anchored to specific adhesion peptide sequences, such as isoleucine-lysine-valine-alanine-valine (IKVAV), a sequence derived from laminin proven to promote cell adhesion and neurite outgrowth, was tested as a useful means to influence nerve regeneration. This approach improves the axonal outgrowth and maintains outgrowth long term. Based on the hypothesis that combinational modulation of substrate topography, stiffness and neurotrophic support, affects axonal outgrowth in whole DRGs, dissociated DRGs were used to assess if these factors similarly act at the single cell level. Rho associated protein kinase (ROCK) and myosin II inhibitors, which affect cytoskeletal contractility, were used to influence growth cone traction forces and have shown that these factors work in combination by interfering with growth cone dynamic creating a different response in axonal outgrowth at the single cell level.

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.