2 resultados para PATTERNED GAAS

em Glasgow Theses Service


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This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.

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The primary objective of this research was to perform an in vitro assessment of the ability of microscale topography to alter cell behaviour, with specific regard to producing favourable topography in an orthopaedic ceramic material suitable for implantation in the treatment of arthritis. Topography at microscale and nanoscale alters the bioactivity of the material. This has been used in orthopaedics for some time as seen with optimal pore size in uncemented hip and knee implants. This level of topography involves scale in hundreds of micrometres and allows for the ingrowth of tissue. Topography at smaller scale is possible thanks to progressive miniaturisation of technology. A topographic feature was created in a readily available clinically licensed polymer, Polycaprolcatone (PCL). The effect of this topography was assessed in vitro. The same topography was transferred to the latest generation composite orthopaedic ceramic, zirconia toughened alumina (ZTA). The fidelity of reproduction of the topography was examined using scanning electron microscopy (SEM) and atomic force microscopy (AFM). These investigations showed more accurate reproduction of the topography in PCL than ZTA with some material artefacts in the ZTA. Cell culture in vitro was performed on the patterned substrates. The response of osteoprogenitor cells was assessed using immunohistochemistry, real-time polymerase chain reaction and alizarin staining. These results showed a small effect on cell behaviour. Finally metabolic comparison was made of the effects created by the two different materials and the topography in each. The results have shown a reproducible topography in orthopaedic ceramics. This topography has demonstrated a positive osteogenic effect in both polycaprolactone and zirconia toughened alumina across multiple assessment modalities.