Alternating surgeries

This thesis is concerned with the question of when the double branched cover of an alternating knot can arise by Dehn surgery on a knot in S^3. We approach this problem using a surgery obstruction, first developed by Greene, which combines Donaldson's Diagonalization Theorem with the $d$-invariants of Ozsvath and Szabo's Heegaard Floer homology. This obstruction shows that if the double branched cover of an alternating knot or link L arises by surgery on S^3, then for any alternating diagram the lattice associated to the Goeritz matrix takes the form of a changemaker lattice. By analyzing the structure of changemaker lattices, we show that the double branched cover of L arises by non-integer surgery on S^3 if and only if L has an alternating diagram which can be obtained by rational tangle replacement on an almost-alternating diagram of the unknot. When one considers half-integer surgery the resulting tangle replacement is simply a crossing change. This allows us to show that an alternating knot has unknotting number one if and only if it has an unknotting crossing in every alternating diagram. These techniques also produce several other interesting results: they have applications to characterizing slopes of torus knots; they produce a new proof for a theorem of Tsukamoto on the structure of almost-alternating diagrams of the unknot; and they provide several bounds on surgeries producing the double branched covers of alternating knots which are direct generalizations of results previously known for lens space surgeries. Here, a rational number p/q is said to be characterizing slope for K in S^3 if the oriented homeomorphism type of the manifold obtained by p/q-surgery on K determines K uniquely. The thesis begins with an exposition of the changemaker surgery obstruction, giving an amalgamation of results due to Gibbons, Greene and the author. It then gives background material on alternating knots and changemaker lattices. The latter part of the thesis is then taken up with the applications of this theory.

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.