MRI indices of functional recovery following intracerebral implantation of a human neural stem cell line in a pre-clinical model of ischaemic stroke

Stem cell therapy for ischaemic stroke is an emerging field in light of an increasing number of patients surviving with permanent disability. Several allogenic and autologous cells types are now in clinical trials with preliminary evidence of safety. Some clinical studies have reported functional improvements in some patients. After initial safety evaluation in a Phase 1 study, the conditionally immortalised human neural stem cell line CTX0E03 is currently in a Phase 2 clinical trial (PISCES-II). Previous pre-clinical studies conducted by ReNeuron Ltd, showed evidence of functional recovery in the Bilateral Asymmetry test up to 6 weeks following transplantation into rodent brain, 4 weeks after middle cerebral artery occlusion. Resting-state fMRI is increasingly used to investigate brain function in health and disease, and may also act as a predictor of recovery due to known network changes in the post-stroke recovery period. Resting-state methods have also been applied to non-human primates and rodents which have been found to have analogous resting-state networks to humans. The sensorimotor resting-state network of rodents is impaired following experimental focal ischaemia of the middle cerebral artery territory. However, the effects of stem cell implantation on brain functional networks has not previously been investigated. Prior studies assessed sensorimotor function following sub-cortical implantation of CTX0E03 cells in the rodent post-stroke brain but with no MRI assessments of functional improvements. This thesis presents research on the effect of sub-cortical implantation of CTX0E03 cells on the resting- state sensorimotor network and sensorimotor deficits in the rat following experimental stroke, using protocols based on previous work with this cell line. The work in this thesis identified functional tests of appropriate sensitivity for long-term dysfunction suitable for this laboratory, and investigated non-invasive monitoring of physiological variables required to optimize BOLD signal stability within a high-field MRI scanner. Following experimental stroke, rats demonstrated expected sensorimotor dysfunction and changes in the resting-state sensorimotor network. CTX0E03 cells did not improve post-stroke functional outcome (compared to previous studies) and with no changes in resting-state sensorimotor network activity. However, in control animals, we observed changes in functional networks due to the stereotaxic procedure. This illustrates the sensitivity of resting-state fMRI to stereotaxic procedures. We hypothesise that the damage caused by cell or vehicle implantation may have prevented functional and network recovery which has not been previously identified due to the application of different functional tests. The findings in this thesis represent one of few pre-clinical studies in resting-state fMRI network changes post-stroke and the only to date applying this technique to evaluate functional outcomes following a clinically applicable human neural stem cell treatment for ischaemic stroke. It was found that injury caused by stereotaxic injection should be taken into account when assessing the effectiveness of treatment.

The development of planar high-K/III-V p-channel MOSFETs for post-silicon CMOS

Conventional Si complementary-metal-oxide-semiconductor (CMOS) scaling is fast approaching its limits. The extension of the logic device roadmap for future enhancements in transistor performance requires non-Si materials and new device architectures. III-V materials, due to their superior electron transport properties, are well poised to replace Si as the channel material beyond the 10nm technology node to mitigate the performance loss of Si transistors from further reductions in supply voltage to minimise power dissipation in logic circuits. However several key challenges, including a high quality dielectric/III-V gate stack, a low-resistance source/drain (S/D) technology, heterointegration onto a Si platform and a viable III-V p-metal-oxide-semiconductor field-effect-transistor (MOSFET), need to be addressed before III-Vs can be employed in CMOS. This Thesis specifically addressed the development and demonstration of planar III-V p-MOSFETs, to complement the n-MOSFET, thereby enabling an all III-V CMOS technology to be realised. This work explored the application of InGaAs and InGaSb material systems as the channel, in conjunction with Al2O3/metal gate stacks, for p-MOSFET development based on the buried-channel flatband device architecture. The body of work undertaken comprised material development, process module development and integration into a robust fabrication flow for the demonstration of p-channel devices. The parameter space in the design of the device layer structure, based around the III-V channel/barrier material options of In_x≥0.53Ga_1-xAs/In_0.52Al_0.48As and In_x≥0.1Ga_1-xSb/AlSb, was systematically examined to improve hole channel transport. A mobility of 433 cm²/Vs, the highest room temperature hole mobility of any InGaAs quantum-well channel reported to date, was obtained for the In_0.85Ga_0.15As (2.1% strain) structure. S/D ohmic contacts were developed based on thermally annealed Au/Zn/Au metallisation and validated using transmission line model test structures. The effects of metallisation thickness, diffusion barriers and de-oxidation conditions were examined. Contacts to InGaSb-channel structures were found to be sensitive to de-oxidation conditions. A fabrication process, based on a lithographically-aligned double ohmic patterning approach, was realised for deep submicron gate-to-source/drain gap (L_side) scaling to minimise the access resistance, thereby mitigating the effects of parasitic S/D series resistance on transistor performance. The developed process yielded gaps as small as 20nm. For high-k integration on GaSb, ex-situ ammonium sulphide ((NH₄)₂S) treatments, in the range 1%-22%, for 10min at 295K were systematically explored for improving the electrical properties of the Al₂O₃/GaSb interface. Electrical and physical characterisation indicated the 1% treatment to be most effective with interface trap densities in the range of 4 - 10×10¹²cm^-2eV^-1 in the lower half of the bandgap. An extended study, comprising additional immersion times at each sulphide concentration, was further undertaken to determine the surface roughness and the etching nature of the treatments on GaSb. A number of p-MOSFETs based on III-V-channels with the most promising hole transport and integration of the developed process modules were successfully demonstrated in this work. Although the non-inverted InGaAs-channel devices showed good current modulation and switch-off characteristics, several aspects of performance were non-ideal; depletion-mode operation, modest drive current (I_d,sat=1.14mA/mm), double peaked transconductance (g_m=1.06mS/mm), high subthreshold swing (SS=301mV/dec) and high on-resistance (R_on=845kΩ.μm). Despite demonstrating substantial improvement in the on-state metrics of I_d,sat (11×), g_m (5.5×) and R_on (5.6×), inverted devices did not switch-off. Scaling gate-to-source/drain gap (L_side) from 1μm down to 70nm improved I_d,sat (72.4mA/mm) by a factor of 3.6 and gm (25.8mS/mm) by a factor of 4.1 in inverted InGaAs-channel devices. Well-controlled current modulation and good saturation behaviour was observed for InGaSb-channel devices. In the on-state In_0.3Ga_0.7Sb-channel (I_d,sat=49.4mA/mm, g_m=12.3mS/mm, R_on=31.7kΩ.μm) and In_0.4Ga_0.6Sb-channel (I_d,sat=38mA/mm, g_m=11.9mS/mm, R_on=73.5kΩ.μm) devices outperformed the InGaAs-channel devices. However the devices could not be switched off. These findings indicate that III-V p-MOSFETs based on InGaSb as opposed to InGaAs channels are more suited as the p-channel option for post-Si CMOS.