Mid-infrared photonic sensors based on metamaterial structures

In this work three different metallic metamaterials (MMs) structures such as asymmetric split ring resonators (A-SRRs), dipole and split H-shaped (ASHs) structures that support plasmonic resonances have been developed. The aim of the work involves the optimization of photonic sensor based on plasmonic resonances and surface enhanced infrared absorption (SEIRA) from the MM structures. The MMs structures were designed to tune their plasmonic resonance peaks in the mid-infrared region. The plasmonic resonance peaks produced are highly dependent on the structural dimension and polarisation of the electromagnetic (EM) source. The ASH structure particularly has the ability to produce the plasmonic resonance peak with dual polarisation of the EM source. The double resonance peaks produced due to the asymmetric nature of the structures were optimized by varying the fundamental parameters of the design. These peaks occur due to hybridization of the individual elements of the MMs structure. The presence of a dip known as a trapped mode in between the double plasmonic peaks helps to narrow the resonances. A periodicity greater than twice the length and diameter of the metallic structure was applied to produce narrow resonances for the designed MMs. A nanoscale gap in each structure that broadens the trapped mode to narrow the plasmonic resonances was also used. A thickness of 100 nm gold was used to experimentally produce a high quality factor of 18 in the mid-infrared region. The optimised plasmonic resonance peaks was used for detection of an analyte, 17β-estradiol. 17β-estradiol is mostly responsible for the development of human sex organs and can be found naturally in the environment through human excreta. SEIRA was the method applied to the analysis of the analyte. The work is important in the monitoring of human biology and in water treatment. Applying this method to the developed nano-engineered structures, enhancement factors of 10^5 and a sensitivity of 2791 nm/RIU was obtained. With this high sensitivity a figure of merit (FOM) of 9 was also achieved from the sensors. The experiments were verified using numerical simulations where the vibrational resonances of the C-H stretch from 17β-estradiol were modelled. Lastly, A-SRRs and ASH on waveguides were also designed and evaluated. These patterns are to be use as basis for future work.

Data structures for SIMD logic simulation

Due to the growth of design size and complexity, design verification is an important aspect of the Logic Circuit development process. The purpose of verification is to validate that the design meets the system requirements and specification. This is done by either functional or formal verification. The most popular approach to functional verification is the use of simulation based techniques. Using models to replicate the behaviour of an actual system is called simulation. In this thesis, a software/data structure architecture without explicit locks is proposed to accelerate logic gate circuit simulation. We call thus system ZSIM. The ZSIM software architecture simulator targets low cost SIMD multi-core machines. Its performance is evaluated on the Intel Xeon Phi and 2 other machines (Intel Xeon and AMD Opteron). The aim of these experiments is to: • Verify that the data structure used allows SIMD acceleration, particularly on machines with gather instructions ( section 5.3.1). • Verify that, on sufficiently large circuits, substantial gains could be made from multicore parallelism ( section 5.3.2 ). • Show that a simulator using this approach out-performs an existing commercial simulator on a standard workstation ( section 5.3.3 ). • Show that the performance on a cheap Xeon Phi card is competitive with results reported elsewhere on much more expensive super-computers ( section 5.3.5 ). To evaluate the ZSIM, two types of test circuits were used: 1. Circuits from the IWLS benchmark suit [1] which allow direct comparison with other published studies of parallel simulators.2. Circuits generated by a parametrised circuit synthesizer. The synthesizer used an algorithm that has been shown to generate circuits that are statistically representative of real logic circuits. The synthesizer allowed testing of a range of very large circuits, larger than the ones for which it was possible to obtain open source files. The experimental results show that with SIMD acceleration and multicore, ZSIM gained a peak parallelisation factor of 300 on Intel Xeon Phi and 11 on Intel Xeon. With only SIMD enabled, ZSIM achieved a maximum parallelistion gain of 10 on Intel Xeon Phi and 4 on Intel Xeon. Furthermore, it was shown that this software architecture simulator running on a SIMD machine is much faster than, and can handle much bigger circuits than a widely used commercial simulator (Xilinx) running on a workstation. The performance achieved by ZSIM was also compared with similar pre-existing work on logic simulation targeting GPUs and supercomputers. It was shown that ZSIM simulator running on a Xeon Phi machine gives comparable simulation performance to the IBM Blue Gene supercomputer at very much lower cost. The experimental results have shown that the Xeon Phi is competitive with simulation on GPUs and allows the handling of much larger circuits than have been reported for GPU simulation. When targeting Xeon Phi architecture, the automatic cache management of the Xeon Phi, handles and manages the on-chip local store without any explicit mention of the local store being made in the architecture of the simulator itself. However, targeting GPUs, explicit cache management in program increases the complexity of the software architecture. Furthermore, one of the strongest points of the ZSIM simulator is its portability. Note that the same code was tested on both AMD and Xeon Phi machines. The same architecture that efficiently performs on Xeon Phi, was ported into a 64 core NUMA AMD Opteron. To conclude, the two main achievements are restated as following: The primary achievement of this work was proving that the ZSIM architecture was faster than previously published logic simulators on low cost platforms. The secondary achievement was the development of a synthetic testing suite that went beyond the scale range that was previously publicly available, based on prior work that showed the synthesis technique is valid.