"Secretary in Fashion" and "Love-Letters": a study of socio-cultural and pragmatic-linguistic features in the late 17th century English language

Epistolary manuals are conspicuous historical documents for the pedagogy of letter writing; however, their actual usage as manuals by letter writers is unknown. "Secretary in Fashion" by Serre (1668), an epistolary manual, and "Love-Letters between a Nobleman and his Sister" (1684), an epistolary novel attributed to Behn, both give insights into epistolary conventions. Their inception and nature is interesting, considering their historical context. Despite the Restoration of Charles II, 17th century England was in a confused political state; as a result, texts regarding social convention or politics interested contemporary readers (the novel is inspired by a scandal of Lord Grey, an ardent Whig opposing Charles II). Past epistolary studies focus on 18th rather than 17th century manuals; the latter is typically used as supplementary information. Similarly, past epistolary fiction studies focus on 18th century texts; moreover, linguistic studies on Behn and the novel are deficient. Thus, this study addresses the research questions: 1) What are the socio-cultural and pragmaticlinguistic features represented in "Secretary in Fashion"? 2) What are the socio-cultural and pragmatic-linguistic features represented in "Love-Letters between a Nobleman and his Sister", and do any of these features correlate with the features represented in "Secretary in Fashion"? How far do the characteristic linguistic features of "Love-Letters between a Nobleman and his Sister" correlate with the practices recommended by the manual? Both texts were qualitatively analysed from an historical pragmatic perspective, which observes the potential effects of the socio-cultural and historical context. Also, as the texts concern shared discourses, comparisons were made with Gricean and Politeness Theory. The results show that the manual is a typical 17th century epistolary manual, aligning particularly with the "Academies of Complements", as it concerns the social conventions of the gentry. The novel mainly upheld instructions on form and matter; deviations occurred due to the amatory nature of some letters, and the narrative force affecting the style. Unfortunately, neither research question elucidates the actual usage of manuals. However, this study does show the epistolary practices of two writers, within specific contexts. It reveals that their 17th century English language use is affected by socialisation, in terms of social conventions concerning social rank, age, and gender; therefore, context varies language use. Also, their popularity reveals the interests of the 17th century society. Interest in epistolary-related texts, surely piques the interest of the modern reader as to why such epistolary-related texts were interesting.

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.