Reconfigurable computing for Monte Carlo simulations: results and prospects of the Janus project

We describe Janus, a massively parallel FPGA-based computer optimized for the simulation of spin glasses, theoretical models for the behavior of glassy materials. FPGAs (as compared to GPUs or many-core processors) provide a complementary approach to massively parallel computing. In particular, our model problem is formulated in terms of binary variables, and floating-point operations can be (almost) completely avoided. The FPGA architecture allows us to run many independent threads with almost no latencies in memory access, thus updating up to 1024 spins per cycle. We describe Janus in detail and we summarize the physics results obtained in four years of operation of this machine; we discuss two types of physics applications: long simulations on very large systems (which try to mimic and provide understanding about the experimental non equilibrium dynamics), and low-temperature equilibrium simulations using an artificial parallel tempering dynamics. The time scale of our non-equilibrium simulations spans eleven orders of magnitude (from picoseconds to a tenth of a second). On the other hand, our equilibrium simulations are unprecedented both because of the low temperatures reached and for the large systems that we have brought to equilibrium. A finite-time scaling ansatz emerges from the detailed comparison of the two sets of simulations. Janus has made it possible to perform spin glass simulations that would take several decades on more conventional architectures. The paper ends with an assessment of the potential of possible future versions of the Janus architecture, based on state-of-the-art technology.

Fitting model-based psychometric functions to simultaneity and temporal-order judgment data: MATLAB and R routines

Research on temporal-order perception uses temporal-order judgment (TOJ) tasks or synchrony judgment (SJ) tasks in their binary SJ2 or ternary SJ3 variants. In all cases, two stimuli are presented with some temporal delay, and observers judge the order of presentation. Arbitrary psychometric functions are typically fitted to obtain performance measures such as sensitivity or the point of subjective simultaneity, but the parameters of these functions are uninterpretable. We describe routines in MATLAB and R that fit model-based functions whose parameters are interpretable in terms of the processes underlying temporal-order and simultaneity judgments and responses. These functions arise from an independent-channels model assuming arrival latencies with exponential distributions and a trichotomous decision space. Different routines fit data separately for SJ2, SJ3, and TOJ tasks, jointly for any two tasks, or also jointly for the three tasks (for common cases in which two or even the three tasks were used with the same stimuli and participants). Additional routines provide bootstrap p-values and confidence intervals for estimated parameters. A further routine is included that obtains performance measures from the fitted functions. An R package for Windows and source code of the MATLAB and R routines are available as Supplementary Files.

Low spatial frequency filtering modulates early brain processing of affective complex pictures

Recent research on affective processing has suggested that low spatial frequency information of fearful faces provide rapid emotional cues to the amygdala, whereas high spatial frequencies convey fine-grained information to the fusiform gyrus, regardless of emotional expression. In the present experiment, we examined the effects of low (LSF, <15 cycles/image width) and high spatial frequency filtering (HSF, >25 cycles/image width) on brain processing of complex pictures depicting pleasant, unpleasant, and neutral scenes. Event-related potentials (ERP), percentage of recognized stimuli and response times were recorded in 19 healthy volunteers. Behavioral results indicated faster reaction times in response to unpleasant LSF than to unpleasant HSF pictures. Unpleasant LSF pictures and pleasant unfiltered pictures also elicited significant enhancements of P1 amplitudes at occipital electrodes as compared to neutral LSF and unfiltered pictures, respectively; whereas no significant effects of affective modulation were found for HSF pictures. Moreover, mean ERP amplitudes in the time between 200 and 500ms post-stimulus were significantly greater for affective (pleasant and unpleasant) than for neutral unfiltered pictures; whereas no significant affective modulation was found for HSF or LSF pictures at those latencies. The fact that affective LSF pictures elicited an enhancement of brain responses at early, but not at later latencies, suggests the existence of a rapid and preattentive neural mechanism for the processing of motivationally relevant stimuli, which could be driven by LSF cues. Our findings confirm thus previous results showing differences on brain processing of affective LSF and HSF faces, and extend these results to more complex and social affective pictures.

A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems

Reconfigurable hardware can be used to build a multitasking system where tasks are assigned to HW resources at run-time according to the requirements of the running applications. These tasks are frequently represented as direct acyclic graphs and their execution is typically controlled by an embedded processor that schedules the graph execution. In order to improve the efficiency of the system, the scheduler can apply prefetch and reuse techniques that can greatly reduce the reconfiguration latencies. For an embedded processor all these computations represent a heavy computational load that can significantly reduce the system performance. To overcome this problem we have implemented a HW scheduler using reconfigurable resources. In addition we have implemented both prefetch and replacement techniques that obtain as good results as previous complex SW approaches, while demanding just a few clock cycles to carry out the computations. We consider that the HW cost of the system (in our experiments 3% of a Virtex-II PRO xc2vp30 FPGA) is affordable taking into account the great efficiency of the techniques applied to hide the reconfiguration latency and the negligible run-time penalty introduced by the scheduler computations.