Implementación sobre FPGA de un algoritmo de compresión de imágenes hiperespectrales bajo el estándar CCSDS 123.0-B-1

A lo largo de la historia, nuestro planeta ha atravesado numerosas y diferentes etapas. Sin embargo, desde finales del cretácico no se vivía un cambio tan rápido como el actual. Y a la cabeza del cambio, nosotros, el ser humano. De igual manera que somos la causa, debemos ser también la solución, y el análisis a gran escala de la tierra está siendo un punto de interés para la comunidad científica en los últimos años. Prueba de ello es que, cada vez con más frecuencia, se lanzan gran cantidad de satélites cuya finalidad es el análisis, mediante fotografías, de la superficie terrestre. Una de las técnicas más versátiles para este análisis es la toma de imágenes hiperespectrales, donde no solo se captura el espectro visible, sino numerosas longitudes de onda. Suponen, eso sí un reto tecnológico, pues los sensores consumen más energía y las imágenes más memoria, ambos recursos escasos en el espacio. Dado que el análisis se hace en tierra firme, es importante una transmisión de datos eficaz y rápida. Por ello creemos que la compresión en tiempo real mediante FPGAs es la solución idónea, combinando un bajo consumo con una alta tasa de compresión, posibilitando el análisis ininterrumpido del astro en el que vivimos. En este trabajo de fin de grado se ha realizado una implementación sobre FPGA, utilizando VHDL, del estándar CCSDS 123. Este está diseñado para la compresión sin pérdida de imágenes hiperespectrales, y permite una amplia gama de configuraciones para adaptarse de manera óptima a cualquier tipo de imagen. Se ha comprobado exitosamente la validez de la implementación comparando los resultados obtenidos con otras implementaciones (software) existentes. Las principales ventajas que presentamos aquí es que se posibilita la compresión en tiempo real, obteniendo además un rendimiento energético muy prometedor. Estos resultados mejoran notablemente los de una implementación software del algoritmo, y permitirán la compresión de las imágenes a bordo de los satélites que las toman.

A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems

New generation embedded systems demand high performance, efficiency and flexibility. Reconfigurable hardware can provide all these features. However the costly reconfiguration process and the lack of management support have prevented a broader use of these resources. To solve these issues we have developed a scheduler that deals with task-graphs at run-time, steering its execution in the reconfigurable resources while carrying out both prefetch and replacement techniques that cooperate to hide most of the reconfiguration delays. In our scheduling environment task-graphs are analyzed at design-time to extract useful information. This information is used at run-time to obtain near-optimal schedules, escaping from local-optimum decisions, while only carrying out simple computations. Moreover, we have developed a hardware implementation of the scheduler that applies all the optimization techniques while introducing a delay of only a few clock cycles. In the experiments our scheduler clearly outperforms conventional run-time schedulers based on As-Soon-As-Possible techniques. In addition, our replacement policy, specially designed for reconfigurable systems, achieves almost optimal results both regarding reuse and performance.

A Task-Graph Execution Manager for Reconfigurable Multi-tasking Systems

Reconfigurable hardware can be used to build multi tasking systems that dynamically adapt themselves to the requirements of the running applications. This is especially useful in embedded systems, since the available resources are very limited and the reconfigurable hardware can be reused for different applications. In these systems computations are frequently represented as task graphs that are executed taking into account their internal dependencies and the task schedule. The management of the task graph execution is critical for the system performance. In this regard, we have developed two dif erent versions, a software module and a hardware architecture, of a generic task-graph execution manager for reconfigurable multi-tasking systems. The second version reduces the run-time management overheads by almost two orders of magnitude. Hence it is especially suitable for systems with exigent timing constraints. Both versions include specific support to optimize the reconfiguration process.

Synchronization of Heteroclinic Circuits Through Learning in Chains of Neural Motifs

The synchronization of oscillatory activity in networks of neural networks is usually implemented through coupling the state variables describing neuronal dynamics. In this study we discuss another but complementary mechanism based on a learning process with memory. A driver network motif, acting as a teacher, exhibits winner-less competition (WLC) dynamics, while a driven motif, a learner, tunes its internal couplings according to the oscillations observed in the teacher. We show that under appropriate training the learner motif can dynamically copy the coupling pattern of the teacher and thus synchronize oscillations with the teacher. Then, we demonstrate that the replication of the WLC dynamics occurs for intermediate memory lengths only. In a unidirectional chain of N motifs coupled through teacher-learner paradigm the time interval required for pattern replication grows linearly with the chain size, hence the learning process does not blow up and at the end we observe phase synchronized oscillations along the chain. We also show that in a learning chain closed into a ring the network motifs come to a consensus, i.e. to a state with the same connectivity pattern corresponding to the mean initial pattern averaged over all network motifs.