4 resultados para semantic frames
em Chinese Academy of Sciences Institutional Repositories Grid Portal
Resumo:
Protein tyrosine phosphatases (PTPs) are comprised of two superfamilies, the phosphatase I superfamily containing a single low-molecular-weight PTP (lmwPTP) family and the phosphatase II superfamily including both the higher-molecular-weight PTP (hmwPTP) and the dual-specificity phosphatase (DSP) families. The phosphatase I and H superfamilies are often considered to be the result of convergent evolution. The PTP sequence and structure analyses indicate that lmwPTPs, hmwPTPs, and DSPs share similar structures, functions, and a common signature motif, although they have low sequence identities and a different order of active sites in sequence or a circular permutation. The results of this work suggest that lmwPTPs and hmwPTPs/DSPs are remotely related in evolution. The earliest ancestral gene of PTPs could be from a short fragment containing about 90similar to120 nucleotides or 30similar to40 residues; however, a probable full PTP ancestral gene contained one transcript unit with two lmwPTP genes. All three PTP families may have resulted from a common ancestral gene by a series of duplications, fusions, and circular permutations. The circular permutation in PTPs is caused by a reading frame difference, which is similar to that in DNA methyltransferases. Nevertheless, the evolutionary mechanism of circular permutation in PTP genes seems to be more complicated than that in DNA methyltransferase genes. Both mechanisms in PTPs and DNA methyltransferases can be used to explain how some protein families and superfamilies came to be formed by circular permutations during molecular evolution.
Resumo:
A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE) array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames/s (fps). A prototype chip with 64 x 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 mu m Standard CMOS process. The area size of chip is 1.5 mm x 3.5 mm. Each pixel size is 9.5 mu m x 9.5 mu m and each processing element size is 23 mu m x 29 mu m. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking.
Resumo:
Ontologies play a core role to provide shared knowledge models to semantic-driven applications targeted by Semantic Web. Ontology metrics become an important area because they can help ontology engineers to assess ontology and better control project management and development of ontology based systems, and therefore reduce the risk of project failures. In this paper, we propose a set of ontology cohesion metrics which focuses on measuring (possibly inconsistent) ontologies in the context of dynamic and changing Web. They are: Number of Ontology Partitions (NOP), Number of Minimally Inconsistent Subsets (NMIS) and Average Value of Axiom Inconsistencies (AVAI). These ontology metrics are used to measure ontological semantics rather than ontological structure. They are theoretically validated for ensuring their theoretical soundness, and further empirically validated by a standard test set of debugging ontologies. The related algorithms to compute these ontology metrics also are discussed. These metrics proposed in this paper can be used as a very useful complementarity of existing ontology cohesion metrics.