CFD结合降阶模型预测阵风响应

传统的阵风响应主要在频域内进行分析，气动载荷基于线性方法计算，不能考虑黏性和跨声速流动影响．飞机设计需考虑不同频率和不同形状阵风的响应，基于CFD的阵风响应预测由于计算工况太多，工作量巨大．本文发展了一种CFD结合非定常气动力ARMA（autoregressive—moving—averagemodel）降阶模型的阵风响应分析方法，CFD只要针对给定频率和形状的一种阵风响应进行计算，对获得的气动力时间历程运用线性最小二乘法参数辨识ARMA降阶模型的系数，则对任意频率和形状的阵风，代入降阶模型即可确定该阵风的响应，大大提高了计算效率．为效验发展的方法，先计算NACA0012翼型在低马赫数0．11的阵风响应，通过对比CFD、ARMA降阶模型及早期发展的不可压阵风响应预测方法的结果，验证了方法的有效性．再对比CFD、ARMA在跨声速马赫数0．8的阵风响应预测结果，证实所发展的方法对跨声速阵风响应预测亦是有效的．

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

Highly efficient single-emitting-layer white organic light-emitting diodes with reduced efficiency roll-off

By codoping blue and orange phosphorescent dyes into a single host material, a highly efficient white organic light-emitting diode (WOLED) with Commission Internationale de L'Eclairage coordinates of (0.38, 0.43) at 12 V is demonstrated. Remarkably, this WOLED achieves reduced current efficiency roll-off, which slightly decreases from its maximum value of 37.3-31.0 cd/A at 1000 cd/m(2). The device operational mechanism is subsequently investigated in order to unveil the origin of the high performance.