Packing LUT clusters with network flow programming

This paper describes a two-step packing algorithm for LUT clusters of which the LUT input multipliers are depopulated. In the first step, a greedy algorithm is used to search for BLE locations and cluster inputs. If the greedy algorithm fails, the second step with network flow programming algorithm is employed. Numerical results illustrate that our two-step packing algorithm obtains better packing density than one-step greedy packing algorithm.

A VSLMS Style Tap-length Learning Algorithm for Structure Adaptation

Compared with the ordinary adaptive filter, the variable-length adaptive filter is more efficient (including smaller., lower power consumption and higher computational complexity output SNR) because of its tap-length learning algorithm, which is able to dynamically adapt its tap-length to the optimal tap-length that best balances the complexity and the performance of the adaptive filter. Among existing tap-length algorithms, the LMS-style Variable Tap-Length Algorithm (also called Fractional Tap-Length Algorithm or FT Algorithm) proposed by Y.Gong has the best performance because it has the fastest convergence rates and best stability. However, in some cases its performance deteriorates dramatically. To solve this problem, we first analyze the FT algorithm and point out some of its defects. Second, we propose a new FT algorithm called 'VSLMS' (Variable Step-size LMS) Style Tap-Length Learning Algorithm, which not only uses the concept of FT but also introduces a new concept of adaptive convergence slope. With this improvement the new FT algorithm has even faster convergence rates and better stability. Finally, we offer computer simulations to verify this improvement.

Design and Verification of the Programming Circuit in an Application-Specific FPGA

In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal. Even though our focus is on the programming circuitry that provides the interface between the FPGA core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the FPGA family. The method presented here covers the generation of the design RTL files and the support files for synthesis, place-and-route layout and simulations. The proposed method is proven to work smoothly within the complete chip design methodology. We will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. Different package options and different programming modes are included in the description of the design. The circuit design implementation is based on SMIC 0.13-micron CMOS technology.

yet another meta-language for programming language processing

The formal specification language LFC was designed to support formal specification acquisition. However, it is yet suited to be used as a meta-language for specifying programming language processing. This paper introduces LFC as a meta-language, and compares it with ASF+SDF, an algebraic specification formalism that can also be used to programming languages.

Optimization of Global Signal Networks for Island-Style FPGAs

We present a staggered buffer connection method that provides flexibility for buffer insertion while designing global signal networks using the tile-based FPGA design methodology. An exhaustive algorithm is used to analyze the trade-off between area and speed of the global signal networks for this staggered buffer insertion scheme, and the criterion for determining the design parameters is presented. The comparative analytic result shows that the methods in this paper are proven to be more efficient for FPGAs with a large array size.

函数式语言方法在网络交互程序中的应用

网络应用程序中为了保持程序的交互性,服务器端的控制程序如CGI(command gateway interface)程序需要在不同的脚本程序之问切换,这样不可避免的会造成控制信息的丢失.为了避免这些问题,介绍了将函数式程序设计语言的一些方法,如Continuation、CPS(eontinuationpassing style)等,并将它们应用到网络程序设计中,不仅简化了设计过程,也提高了程序的安全性,并可以在更一般的语言中实现.

extending the boundary of spreadsheet programming: lessons learned from chinese governmental projects

ICSE

聚类引导搜索的移动机器人路径规划方法

本文提出一种聚类引导搜索（cluster guide searching，CGS）的路径规划方法。采用基于最大最小距离的K均值聚类方法对样本进行离线聚类学习，学习结果以相似环境相似决策的知识形式进行存储。路径规划过程中，机器人在线整理环境信息，获得输入空间样本，通过与知识库匹配，检索到最近的类别，然后在该类别内部采用速度优先策略和方向优先策略交替的方式搜索输出空间。若知识不完备导致检索失败，可重启线性规划算法（linear programming，LP）进行在线路径规划，并更新聚类知识库。仿真结果表明该方法是一种有效的路径规划学习方法。

A QUASI-SIMPLEX METHOD FOR STRICTLY CONVEX QUADRATIC PROGRAMMING

本文提出一个不用 Kuhn- Tucker条件而直接搜索严格凸二次规划最优目标点的鲁棒方法 .在搜索过程中 ,目标点沿约束多面体边界上的一条折线移动 .这种移动目标点的思想可以被认为是线性规划单纯形法的自然推广 ,在单纯形法中 ,目标点从一个顶点移到另一个顶点。

双机械臂协调系统的一类最优轨迹规划方法