Design for an IO block array in a tile-based FPGA

A design for an IO block array in a tile-based FPGA is presented.Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers.Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area.The local routing pool increases the flexibility of routing and the routability of the whole FPGA.An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards.The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool.This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series.The bond-out schemes of the same FPGA chip in different packages are also considered.The layout is based on SMIC 0.13μm logic 1P8M salicide 1.2/2.5 V CMOS technology.Our performance is comparable with commercial SRAM-based FPGAs which use a similar process.

Ultrathin platinum-group metal coated hierarchical flowerlike gold microstructure: Electrochemical design and characterization

The deliberate tailoring of hierarchical flowerlike gold microstructure (HFGMs) at the ultrathin level is an ongoing challenge and could introduce opportunities for new fabrication and application in many fields. In this paper. a templateless, surfactantless, electrochemical strategy for fabrication of ultrathin platinum-group metal coated HFGMs is proposed. HFGMs were prepared by simple electrodeposition on an indium tin oxide (ITO) substrate.