用VHDL实现的23位快速浮点数加减法器

With the development of LSI, FPGA/CPLD has been used more and more in the fields of digital signal processing and au-tocontrol and so on. And with the development of the techniques of digital processing, for fitting the system’s function, it should be a higher requirement to speed and used-resource to compute the floating point numbers. The author introduces a high speed adder-subtracter of the 23 bit’s floating point numbers, which is carried out with the parallel arithmetic and the computational speed cou...中文文摘：随着大规模集成电路的不断发展,FPGA/CPLD在数字信号处理、自动控制等方面得到了越来越多的应用。并且伴随着数字化处理技术的不断发展,为满足系统功能的要求,对浮点数运算的速度以及相应占用的资源也就提出了更高的要求。笔者即介绍了以VHDL语言为基础,采用并行算法且计算速度达到33MHz的,对23位标准浮点数实现的高速浮点加减法运算器,并以Cyclone II芯片EP2C20F484为硬件环境,最终进行时序模拟仿真,从而验证该浮点加减法器的正确性和快速特性。

时变带限信道中光通信的均衡与去噪技术

A semi-blind equalization method is proposed based on combination of adaptive and blind equalization techniques, which is more effective for optical signal processing in time-varied band-limited channel. The numerical simulation of Poisson noise OOK optical pulse signal in a band-limited channel using digital equalization techniques is performed, and the results are compared. The semi-blind equalization matchs the channel faster and sustains convergence were identified. In addition, the wavelet de-noise technique is introduced in the de-nosing area of optical signa process. The criteria of choosing wavelet basises is obtained that smooth wavelet soft threshold method is better. The corresponding numerical simulation is also conducted.

电机转速自适应测量方法及其在DSP上的实现

本文在分析几种常用的基于编码器测速方法的基础上,提出了一种高性能的自适应速度测量方法。该方法选择一个可变的时间周期和编码器脉冲数来测量单位时间内的编码器脉冲数,再通过简单的计算得到转速的测量值。数字信号处理器(DSP)芯片集成有正交脉冲编码电路,并且数据处理速度快,实时性强。本文中提出的方法在电机控制专用DSP芯片TMS320 LF2407A上进行了实现。实验研究表明,可以在提高低速时的测速准确度的同时,提高系统的响应时间。该方法已经在自主研发的全数字伺服驱动系统中得到了成功应用。