星载激光测距仪的高精度时间间隔测量单元

高精度时间间隔测量单元(TIU)是星载激光测距仪的关键部件。基于现场可编程门阵列(FPGA)研制出了满足星载要求的高精度、高集成度时间间隔测量单元。该单元采用数字计数法结合数字延迟线插入法的技术,在0.5～10 km的测量距离范围内,时间分辨率为500 ps。通过地面检测,在全程范围内保持了良好的线性度,标准偏差小于270 ps。该单元同时具备测量脉冲回波宽度的能力,可以获取目标的脉冲展宽信息。由于单元选用的元器件都具有航天产品性能,因此其设计和技术指标可满足星载激光测距仪的应用。

Restoration of the signals from multi-hit three-layer delay-line anode position-sensitive detector

Multi-hit 3-layer delay-line anode (Hexanode) has an increased ability to detect multi-hit events in a collision experiment. Coupled with a pair of micro-channel plates, it can provide position information of the particles even if the particles arrive at the same time or within small time dwell. But it suffers from some ambiguous outputs and signal losses due to timing order and triggering thresholds etc. We have developed a signal reconstruction program to correct those events. After the program correction, the dead time only exists when 2 paxticles arrive at the same time and the same position within a much smaller range. With the combination of Hexanode and the program, the experimental efficiencies will be greatly improved in near threshold double ionization on He collisions.

用于高能轻粒子探测的延迟线PPAC(英文)；Delay-line PPAC for Intermediate Energy Light Ions

气体探测器有成本低廉、制备简单、性能可靠和方便使用等特点。研制了一种5层板结构的延迟线平行板雪崩电离室(PPAC),用于兰州放射性束流线(RIBLL)上开展的实验。在57.6MeV/u的6He束流条件下测试了这种探测器对高能轻粒子的适用性,得到了位置分辨为1.8mm(FWHM),时间分辨为2.6ns,以及可靠的探测效率。

用于机载激光测深系统的时间间隔测量模块

机载海洋激光测深系统不仅要求精确测量激光从海表的入射点到海底目标点之间的距离，还要精确测定飞机到海表入射，点之间的距离，为水深数据的海浪校正而确定平均海平面以及波高。为此设计和研制了一高精度时间间隔测量器，该单元基于专用时间数字转换芯片开发，采用延迟线插入法技术，双通道工作，具有高时间分辨率(最高可达250ps)和高测量重复率的特性。给出硬件和软件设计方法以及单元的测试结果。

Kicker电源数字延迟线及低压监测系统设计

踢轨磁铁（Kicker）电源系统是HIRFL-CSR注入引出系统中实现快引出的一个关键元件，主要功能是为踢轨磁铁提供快脉冲励磁电流以产生所需要的快脉冲磁场。Kicker电源提供的是高电压大电流的快脉冲，电流脉冲上升沿和下降沿为150ns,脉冲宽度为650ns,其脉冲峰值电流为2700A，工作周期为10s-17s。因此及时监控Kicker电源闸流管的工作状况以及电流脉冲波形特性至关重要。本文针对踢轨磁铁（Kicker）电源的需要，进行了Kicker电源监测系统的设计，主要针对闸流管误漏导通检测、电流脉冲宽度过宽过窄检测、脉冲宽度测量及脉冲计数等功能提出了电路的工作原理，并设计了具体电路。系统输入端采用光纤接口，而输出端采用了PLC数字I/O接口。由于采用PLC接收监测电路板的信号来完成对Kicker电源的监控报警，基于此编写了相关PLC程序，并调试通过。该监测系统电路板已调试完成，可以很好地完成对Kicker电源系统较为全面的状态监测，方便地对Kicker电源系统状态进行监控。另外，为了解决Kicker电源系统脉冲同步的问题，以满足兰州重离子加速器冷却储存环（HIRFL-CSR）环踢轨磁铁（Kicker）电源对电流脉冲进行适当延迟的要求，还分别设计了ECL高速可程控数字延迟线电路系统和基于CPLD的数字延迟线系统，分析介绍了数字延迟线系统结构、工作原理及PCB版图设计等。ECL高速可程控数字延迟线电路已初步调试通过，而基于CPLD的数字延迟线系统已完成了程序编程及仿真工作，它克服了ECL数字延迟线不能实现零延迟的缺点，且可以通过修改VHDL程序来设置出更多位的可编程数字延迟线，方便灵活

Kicker电源数字延迟线及低压监测系统设计

踢轨磁铁（Kicker）电源系统是兰州重离子加速器冷却储存环（HIRFL-CSR）注入引出系统中实现快引出的一个关键元件，主要功能是为踢轨磁铁提供快脉冲励磁电流以产生所需要的快脉冲磁场。踢轨磁铁（Kicker）电源系统各触发脉冲是否同步关系到束流能否顺利注入引出以及有好的束流品质。基于此，本文介绍了基于CPLD-EPM1270T144的数字延迟线系统，以满足HIRFL-CSR踢轨磁铁（Kicker）电源对触发脉冲进行适当延迟的要求；分析介绍了数字延迟线系统结构、工作原理、PCB制版及系统调试。实际检验证明本设计通过修改VHDL程序来调节延迟时间能够方便灵活的完成Kicker电源系统对脉冲同步的要求，延迟精度达到10ns。另外，由于Kicker电源提供的是高电压大电流的快脉冲，电流脉冲上升沿和下降沿为150ns、脉冲宽度为650ns,其脉冲峰值电流为2700A、工作周期为10s-17s，因此及时监控Kicker电源闸流管的工作状况以及电流脉冲波形特性非常重要。基于此，本文还进行了Kicker电源监测系统的设计。该设计主要针对闸流管误漏导通检测、电流脉冲宽度过宽过窄检测、脉冲宽度测量及脉冲计数等功能提出了电路的系统结构、工作原理，并完成了程序编程、仿真及外围电路设计

Controllable negative and positive group delay in transmission through a single quantum well at finite magnetic fields

We investigate the controllable negative and positive group delay in transmission through a single quantum well at the finite longitudinal magnetic fields. It is shown that the magneto-coupling effect between the longitudinal motion component and the transverse Landau orbits plays an important role in the group delay. The group delay depends not only on the width of potential well and the incident energy, but also on the magnetic-field strengthen and the Landau quantum number. The results show that the group delay can be changed from positive to negative by the modulation of the magnetic field. These interesting phenomena may lead to the tunable quantum mechanical delay line. (c) 2007 Elsevier B.V. All rights reserved.

Lineshape Analysis of the Beat Signal Between Optical Carrier and Delayed Sidebands

This paper presents the lineshape analysis of the beat signal between the optical carrier and the shifted and delayed side-bands produced by sinusoidal amplitude modulation. It is shown that the beat signal has a typical lineshape with a very narrow delta-peak superposed on a quasi-Lorentzian profile. Theoretical explanation for the appearance of this peak has been given based on optical spectral structure constructed by a large number of optical wave trains. It is predicted that the delta-peak is originated from the beat between the wave trains in the carrier and those in the delayed sidebands when their average coherence length is longer than the delay line. Experiments carried out using different delay lines clearly show that the delta-peak is always located at the modulation frequency and decreases with the increasing delay line. Our analysis explicitly indicates that the linewidth is related to the observation time. It is also suggested that the disappearance of the delta-peak can be used as the criterion of coherence elimination.

Phase uncertainty in calibrating microwave test fixtures

The problem of phase uncertainty arising in calibration of the test fixtures is investigated in this paper, It is shown that the problem exists no matter what kinds of calibration standards are used. It is also found that there is no need to determine the individual S-parameters of the test fixtures. In order to eliminate the problem of phase uncertainty, three different precise (known) reflection standards or one known reflection standard plus one known transmission standard should be used to calibrate symmetrical test fixtures. For the asymmetrical cases, three known standards, including at least one transmission standard, should be used. The thru-open-match (TOM) and thru-short-match (TSM) techniques are the simplest methods, and they have no bandwidth limitation. When the standards are imprecise (unknown), it is recommended to use any suitable technique, such as the thru-reflect-line, line-reflect-line, thru-short-delay, thru-open-delay,line-reflect-match, line-reflect-reflect-match, or multiline methods, to accurately determine the values of the required calibration terms and, in addition, to use the TOM or TSM method with the same imprecise standards to resolve the phase uncertainty.

Low-timing-jitter, stretched-pulse passively mode-locked fiber laser with tunable repetition rate and high operation stability

We design a low-timing-jitter, repetition-rate-tunable, stretched-pulse passively mode-locked fiber laser by using a nonlinear amplifying loop mirror (NALM), a semiconductor saturable absorber mirror (SESAM), and a tunable optical delay line in the laser configuration. Low-timing-jitter optical pulses are stably produced when a SESAM and a 0.16 m dispersion compensation fiber are employed in the laser cavity. By inserting a tunable optical delay line between NALM and SESAM, the variable repetition-rate operation of a self-starting, passively mode-locked fiber laser is successfully demonstrated over a range from 49.65 to 50.47 MHz. The experimental results show that the newly designed fiber laser can maintain the mode locking at the pumping power of 160 mW to stably generate periodic optical pulses with width less than 170 fs and timing jitter lower than 75 fs in the 1.55 mu m wavelength region, when the fundamental repetition rate of the laser is continuously tuned between 49.65 and 50.47 MHz. Moreover, this fiber laser has a feature of turn-key operation with high repeatability of its fundamental repetition rate in practice.

基于数字制造环境的可重构装配线仿真分析平台

以某汽车变速箱装配生产线制造系统为背景,应用多Agent制造及Holon制造模式改造传统装配生产线以提升其柔性与重构能力·针对基于agent与holon混合思想的可重构装配生产线的基础框架与实现等理论提供分析验证环境,提出应用数字制造技术构建面向可重构装配线的数字仿真验证平台·在分析面向重构装配线的仿真平台功能特征的基础上,构建了数字仿真验证平台的框架·研究了仿真平台开发中的系统集成、可视化仿真、可重构装配线性能分析等关键技术,最后给出了仿真平台的实例系统·

数字化生产线离散制造过程仿真研究

数字化工厂是目前先进制造技术研究的热点。进行内嵌在生产线数字化制造环境中的离散制造过程仿真研究,建立了面向对象的系统模型,分析了仿真运行机理;同时基于eM-Plant软件开发离散制造过程仿真系统,通过具体的生产线实例说明系统的开发与运行机理,提供数字化生产线离散制造过程仿真研究的有效手段。

地震反射系数成像方法研究

Reflectivity sequences extraction is a key part of impedance inversion in seismic exploration. Although many valid inversion methods exist, with crosswell seismic data, the frequency brand of seismic data can not be broadened to satisfy the practical need. It is an urgent problem to be solved. Pre-stack depth migration which developed in these years becomes more and more robust in the exploration. It is a powerful technology of imaging to the geological object with complex structure and its final result is reflectivity imaging. Based on the reflectivity imaging of crosswell seismic data and wave equation, this paper completed such works as follows: Completes the workflow of blind deconvolution, Cauchy criteria is used to regulate the inversion(sparse inversion). Also the precondition conjugate gradient(PCG) based on Krylov subspace is combined with to decrease the computation, improves the speed, and the transition matrix is not necessary anymore be positive and symmetric. This method is used to the high frequency recovery of crosswell seismic section and the result is satisfactory. Application of rotation transform and viterbi algorithm in the preprocess of equation prestack depth migration. In equation prestack depth migration, the grid of seismic dataset is required to be regular. Due to the influence of complex terrain and fold, the acquisition geometry sometimes becomes irregular. At the same time, to avoid the aliasing produced by the sparse sample along the on-line, interpolation should be done between tracks. In this paper, I use the rotation transform to make on-line run parallel with the coordinate, and also use the viterbi algorithm to complete the automatic picking of events, the result is satisfactory. 1. Imaging is a key part of pre-stack depth migration besides extrapolation. Imaging condition can influence the final result of reflectivity sequences imaging greatly however accurate the extrapolation operator is. The author does migration of Marmousi under different imaging conditions. And analyzes these methods according to the results. The results of computation show that imaging condition which stabilize source wave field and the least-squares estimation imaging condition in this paper are better than the conventional correlation imaging condition. The traditional pattern of "distributed computing and mass decision" is wisely adopted in the field of seismic data processing and becoming an obstacle of the promoting of the enterprise management level. Thus at the end of this paper, a systemic solution scheme, which employs the mode of "distributed computing - centralized storage - instant release", is brought forward, based on the combination of C/S and B/S release models. The architecture of the solution, the corresponding web technology and the client software are introduced. The application shows that the validity of this scheme.

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

A Compact Direct Digital Frequency Synthesizer for the Rubidium Atomic Frequency Standard

A compact direct digital frequency synthesizer （DDFS） for system-on-chip implementation of the high precision rubidium atomic frequency standard is developed. For small chip size and low power consumption, the phase to sine mapping data is compressed using sine symmetry technique, sine-phase difference technique, quad line approximation technique,and quantization and error read only memory （QE-ROM） technique. The ROM size is reduced by 98% using these techniques. A compact DDFS chip with 32bit phase storage depth and a 10bit on-chip digital to analog converter has been successfully implemented using a standard 0.35μm CMOS process. The core area of the DDFS is 1.6mm^2. It consumes 167mW at 3.3V,and its spurious free dynamic range is 61dB.